mirror of https://github.com/efabless/caravel.git
143 lines
3.8 KiB
YAML
143 lines
3.8 KiB
YAML
- status: 0 - openlane design prep
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runtime_s: 1.87
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runtime_ts: 0h0m1s873ms
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- status: 1 - synthesis - yosys
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runtime_s: 26.25
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runtime_ts: 0h0m26s254ms
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- status: 2 - sta - openroad
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runtime_s: 1.25
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runtime_ts: 0h0m1s248ms
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- status: 3 - floorplan initialization - openroad
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runtime_s: 0.7
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runtime_ts: 0h0m0s704ms
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- status: 4 - io_place - openlane
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runtime_s: 0.47
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runtime_ts: 0h0m0s465ms
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- status: 5 - tap/decap insertion - openroad
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runtime_s: 0.55
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runtime_ts: 0h0m0s548ms
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- status: 6 - pdn generation - openroad
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runtime_s: 0.8
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runtime_ts: 0h0m0s796ms
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- status: 7 - global placement - openroad
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runtime_s: 12.89
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runtime_ts: 0h0m12s890ms
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- status: 8 - sta - openroad
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runtime_s: 2.27
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runtime_ts: 0h0m2s273ms
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- status: 9 - resizer design optimizations - openroad
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runtime_s: 5.72
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runtime_ts: 0h0m5s716ms
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- status: 10 - detailed placement - openroad
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runtime_s: 0.95
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runtime_ts: 0h0m0s947ms
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- status: 11 - sta - openroad
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runtime_s: 2.13
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runtime_ts: 0h0m2s129ms
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- status: 12 - cts - openroad
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runtime_s: 31.16
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runtime_ts: 0h0m31s164ms
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- status: 13 - sta - openroad
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runtime_s: 4.03
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runtime_ts: 0h0m4s27ms
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- status: 14 - resizer timing optimizations - openroad
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runtime_s: 7.49
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runtime_ts: 0h0m7s493ms
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- status: 15 - resizer design optimizations - openroad
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runtime_s: 46.26
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runtime_ts: 0h0m46s259ms
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- status: 16 - sta - openroad
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runtime_s: 4.32
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runtime_ts: 0h0m4s317ms
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- status: 17 - resizer timing optimizations - openroad
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runtime_s: 32.82
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runtime_ts: 0h0m32s817ms
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- status: 18 - sta - openroad
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runtime_s: 4.71
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runtime_ts: 0h0m4s705ms
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- status: 20 - detailed placement - openroad
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runtime_s: 1.12
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runtime_ts: 0h0m1s121ms
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- status: 20 - io diode insertion - openlane
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runtime_s: 1.23
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runtime_ts: 0h0m1s227ms
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- status: 22 - detailed placement - openroad
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runtime_s: 1.27
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runtime_ts: 0h0m1s270ms
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- status: 22 - heuristic diode insertion - openlane
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runtime_s: 1.39
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runtime_ts: 0h0m1s386ms
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- status: 24 - write verilog - openroad
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runtime_s: 0.95
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runtime_ts: 0h0m0s948ms
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- status: 25 - sta - openroad
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runtime_s: 3.12
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runtime_ts: 0h0m3s121ms
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- status: 25 - global routing - openroad
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runtime_s: 3.12
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runtime_ts: 0h0m3s121ms
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- status: 26 - fill insertion - openroad
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runtime_s: 1.43
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runtime_ts: 0h0m1s429ms
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- status: 27 - detailed_routing - openroad
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runtime_s: 2005.06
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runtime_ts: 0h33m25s64ms
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- status: 28 - wire lengths - openlane
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runtime_s: 0.78
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runtime_ts: 0h0m0s783ms
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- status: 29 - parasitics extraction - openroad
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runtime_s: 5.26
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runtime_ts: 0h0m5s264ms
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- status: 30 - sta - openroad
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runtime_s: 25.57
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runtime_ts: 0h0m25s574ms
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- status: 31 - parasitics extraction - openroad
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runtime_s: 5.44
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runtime_ts: 0h0m5s437ms
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- status: 32 - sta - openroad
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runtime_s: 27.53
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runtime_ts: 0h0m27s525ms
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- status: 33 - parasitics extraction - openroad
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runtime_s: 5.33
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runtime_ts: 0h0m5s331ms
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- status: 34 - sta - openroad
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runtime_s: 25.88
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runtime_ts: 0h0m25s879ms
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- status: 35 - sta - openroad
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runtime_s: 6.66
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runtime_ts: 0h0m6s657ms
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- status: 36 - ir drop report - openroad
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runtime_s: 2.17
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runtime_ts: 0h0m2s165ms
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- status: 37 - gdsii - magic
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runtime_s: 31.98
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runtime_ts: 0h0m31s977ms
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- status: 38 - spice extraction - magic
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runtime_s: 23.73
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runtime_ts: 0h0m23s725ms
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- status: 40 - write verilog - openroad
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runtime_s: 2.6
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runtime_ts: 0h0m2s604ms
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- status: 40 - write powered verilog - openlane
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runtime_s: 2.73
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runtime_ts: 0h0m2s734ms
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- status: 41 - lvs - netgen
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runtime_s: 2.34
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runtime_ts: 0h0m2s337ms
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- status: 42 - drc - magic
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runtime_s: 109.08
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runtime_ts: 0h1m49s75ms
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- status: 43 - antenna check - openroad
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runtime_s: 2.94
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runtime_ts: 0h0m2s944ms
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- status: 44 - erc - circuit validity checker
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runtime_s: 0.37
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runtime_ts: 0h0m0s374ms
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---
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- status: routed
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runtime_s: 2210.0
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runtime_ts: 0h36m50s0ms
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- status: flow completed
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runtime_s: 2491.0
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runtime_ts: 0h41m31s0ms
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