mirror of https://github.com/efabless/caravel.git
196 lines
3.8 KiB
ArmAsm
Executable File
196 lines
3.8 KiB
ArmAsm
Executable File
/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*-----------------------------------------------*/
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/* Start code that enables and handles an IRQ */
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/*-----------------------------------------------*/
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#undef ENABLE_FASTIRQ
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#include "custom_ops.S"
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.section .text
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.global irq
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reset_vec:
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j start
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/* Interrupt handler @ 0x10000004 */
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/* Requires defining a routine called irq_callback in the C code */
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.balign 4
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irq_vec:
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sw gp, 0*4+0x10(zero)
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sw t0, 1*4+0x10(zero)
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sw t1, 2*4+0x10(zero)
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sw t2, 3*4+0x10(zero)
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sw t4, 4*4+0x10(zero)
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sw t5, 5*4+0x10(zero)
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call irq_callback
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lw gp, 0*4+0x10(zero)
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lw t0, 1*4+0x10(zero)
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lw t1, 2*4+0x10(zero)
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lw t2, 3*4+0x10(zero)
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lw t4, 4*4+0x10(zero)
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lw t5, 5*4+0x10(zero)
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picorv32_retirq_insn()
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irq_regs:
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.fill 32,8
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/* Main program */
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start:
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# zero-initialize register file
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addi x1, zero, 0
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# x2 (sp) is initialized by reset
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addi x3, zero, 0
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addi x4, zero, 0
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addi x5, zero, 0
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addi x6, zero, 0
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addi x7, zero, 0
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addi x8, zero, 0
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addi x9, zero, 0
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addi x10, zero, 0
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addi x11, zero, 0
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addi x12, zero, 0
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addi x13, zero, 0
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addi x14, zero, 0
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addi x15, zero, 0
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addi x16, zero, 0
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addi x17, zero, 0
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addi x18, zero, 0
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addi x19, zero, 0
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addi x20, zero, 0
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addi x21, zero, 0
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addi x22, zero, 0
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addi x23, zero, 0
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addi x24, zero, 0
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addi x25, zero, 0
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addi x26, zero, 0
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addi x27, zero, 0
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addi x28, zero, 0
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addi x29, zero, 0
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addi x30, zero, 0
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addi x31, zero, 0
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# zero initialize scratchpad memory
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# setmemloop:
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# sw zero, 0(x1)
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# addi x1, x1, 4
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# blt x1, sp, setmemloop
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# Write these instructions to memory location zero and following:
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# lui t4, 0x10000 = 10000eb7
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# addi t4, t4, 4 = 0e91
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# jalr t4, 0 = 000e80e7
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#
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# These three instructions jump to 0x10000004, which is the location
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# of the interrupt handler. For a fast interrupt handler, the whole
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# handler should be moved into SRAM.
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li t4, 0x10000eb7
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sw t4, 0(zero)
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li t4, 0x80e70e91
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sw t4, 4(zero)
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li t4, 0x000e
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sw t4, 8(zero)
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# Enable the timer IRQ only
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li t4, 0xfff0
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picorv32_maskirq_insn(t4, t4)
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# Set the picorv32 32-bit counter/timer to trigger one interrupt.
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li t4, 0x1200
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picorv32_timer_insn(t4, t4)
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# call main
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call main
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loop:
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j loop
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.global flashio_worker_begin
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.global flashio_worker_end
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flashio_worker_begin:
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# a0 ... data pointer
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# a1 ... data length
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# a2 ... optional WREN cmd (0 = disable)
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# address of SPI ctrl reg
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li t0, 0x02000000
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# Set CS high, IO0 is output
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li t1, 0x120
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sh t1, 0(t0)
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# Enable Manual SPI Ctrl
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sb zero, 3(t0)
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# Send optional WREN cmd
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beqz a2, flashio_worker_L1
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li t5, 8
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andi t2, a2, 0xff
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flashio_worker_L4:
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srli t4, t2, 7
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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slli t2, t2, 1
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andi t2, t2, 0xff
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addi t5, t5, -1
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bnez t5, flashio_worker_L4
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sb t1, 0(t0)
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# SPI transfer
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flashio_worker_L1:
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beqz a1, flashio_worker_L3
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li t5, 8
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lbu t2, 0(a0)
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flashio_worker_L2:
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srli t4, t2, 7
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sb t4, 0(t0)
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ori t4, t4, 0x10
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sb t4, 0(t0)
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lbu t4, 0(t0)
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andi t4, t4, 2
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srli t4, t4, 1
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slli t2, t2, 1
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or t2, t2, t4
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andi t2, t2, 0xff
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addi t5, t5, -1
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bnez t5, flashio_worker_L2
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sb t2, 0(a0)
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addi a0, a0, 1
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addi a1, a1, -1
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j flashio_worker_L1
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flashio_worker_L3:
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# Back to MEMIO mode
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li t1, 0x80
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sb t1, 3(t0)
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ret
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flashio_worker_end:
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