jeffdi 2bc184f5c1 Merge remote-tracking branch 'origin/main' into main		2021-12-16 12:29:44 -08:00
..
dv	adding user_project_wrapper empty files -- gds & lef	2021-12-16 12:29:35 -08:00
gl	Corrected an error in verilog/gl/chip_io_alt.v, which was missing	2021-12-07 10:06:35 -05:00
rtl	Modified simple_por.v RTL to avoid the wire declaration that "cvc"	2021-12-08 12:16:19 -05:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00