caravel/verilog
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
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dv adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
gl [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
rtl Modified simple_por.v RTL to avoid the wire declaration that "cvc" 2021-12-08 12:16:19 -05:00
stubs [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00