mirror of https://github.com/efabless/caravel.git
4496 lines
358 KiB
Plaintext
4496 lines
358 KiB
Plaintext
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Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__nfet_01v8 |Circuit 2: sky130_fd_pr__nfet_01v8
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-------------------------------------------|-------------------------------------------
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1 |1
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2 |2
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3 |3
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4 |4
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
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Circuit 1 cell sky130_fd_pr__pfet_01v8_hvt and Circuit 2 cell sky130_fd_pr__pfet_01v8_hvt are black boxes.
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Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
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Warning: Equate pins: cell sky130_fd_pr__pfet_01v8_hvt is a placeholder, treated as a black box.
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Subcircuit pins:
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Circuit 1: sky130_fd_pr__pfet_01v8_hvt |Circuit 2: sky130_fd_pr__pfet_01v8_hvt
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-------------------------------------------|-------------------------------------------
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1 |1
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2 |2
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3 |3
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4 |4
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_pr__pfet_01v8_hvt and sky130_fd_pr__pfet_01v8_hvt are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
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sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
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Number of devices: 2 |Number of devices: 2
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Number of nets: 4 |Number of nets: 4
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_ef_sc_hd__decap_12 |Circuit 2: sky130_ef_sc_hd__decap_12
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-------------------------------------------|-------------------------------------------
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VPB |VPB
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VNB |VNB
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VPWR |VPWR
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VGND |VGND
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_ef_sc_hd__decap_12 and sky130_ef_sc_hd__decap_12 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
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sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
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Number of devices: 2 |Number of devices: 2
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Number of nets: 4 |Number of nets: 4
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__decap_6 |Circuit 2: sky130_fd_sc_hd__decap_6
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-------------------------------------------|-------------------------------------------
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VPB |VPB
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VNB |VNB
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VPWR |VPWR
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VGND |VGND
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__decap_6 and sky130_fd_sc_hd__decap_6 are equivalent.
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Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VGND
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Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPWR
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Cell sky130_fd_sc_hd__diode_2 (0) disconnected node: VPB
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Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VGND
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Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPB
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Cell sky130_fd_sc_hd__diode_2 (1) disconnected node: VPWR
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__diode_pw2nd_05v5 (1) |sky130_fd_pr__diode_pw2nd_05v5 (1)
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Number of devices: 1 |Number of devices: 1
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Number of nets: 2 |Number of nets: 2
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__diode_2 |Circuit 2: sky130_fd_sc_hd__diode_2
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-------------------------------------------|-------------------------------------------
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VNB |VNB
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DIODE |DIODE
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VGND |VGND
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VPWR |VPWR
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VPB |VPB
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__diode_2 and sky130_fd_sc_hd__diode_2 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
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sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
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Number of devices: 6 |Number of devices: 6
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Number of nets: 9 |Number of nets: 9
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__nand2b_1 |Circuit 2: sky130_fd_sc_hd__nand2b_1
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-------------------------------------------|-------------------------------------------
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Y |Y
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VNB |VNB
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VPWR |VPWR
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VPB |VPB
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A_N |A_N
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VGND |VGND
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B |B
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__nand2b_1 and sky130_fd_sc_hd__nand2b_1 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
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sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
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Number of devices: 2 |Number of devices: 2
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Number of nets: 4 |Number of nets: 4
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__decap_3 |Circuit 2: sky130_fd_sc_hd__decap_3
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-------------------------------------------|-------------------------------------------
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VPB |VPB
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VNB |VNB
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VPWR |VPWR
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VGND |VGND
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__decap_3 and sky130_fd_sc_hd__decap_3 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
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sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
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Number of devices: 2 |Number of devices: 2
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Number of nets: 4 |Number of nets: 4
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__decap_8 |Circuit 2: sky130_fd_sc_hd__decap_8
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-------------------------------------------|-------------------------------------------
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VPB |VPB
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VNB |VNB
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VPWR |VPWR
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VGND |VGND
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__decap_8 and sky130_fd_sc_hd__decap_8 are equivalent.
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Class sky130_fd_sc_hd__and2_4 (0): Merged 6 parallel devices.
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Class sky130_fd_sc_hd__and2_4 (1): Merged 6 parallel devices.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (6->3) |sky130_fd_pr__pfet_01v8_hvt (6->3)
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sky130_fd_pr__nfet_01v8 (6->3) |sky130_fd_pr__nfet_01v8 (6->3)
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Number of devices: 6 |Number of devices: 6
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Number of nets: 9 |Number of nets: 9
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__and2_4 |Circuit 2: sky130_fd_sc_hd__and2_4
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-------------------------------------------|-------------------------------------------
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B |B
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A |A
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VGND |VGND
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X |X
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VPWR |VPWR
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VPB |VPB
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VNB |VNB
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__and2_4 and sky130_fd_sc_hd__and2_4 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
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sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
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Number of devices: 6 |Number of devices: 6
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Number of nets: 9 |Number of nets: 9
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__or2_1 |Circuit 2: sky130_fd_sc_hd__or2_1
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-------------------------------------------|-------------------------------------------
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A |A
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VPWR |VPWR
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X |X
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B |B
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VPB |VPB
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VGND |VGND
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VNB |VNB
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__or2_1 and sky130_fd_sc_hd__or2_1 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__buf_1 |Circuit 2: sky130_fd_sc_hd__buf_1
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
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sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
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Number of devices: 4 |Number of devices: 4
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Number of nets: 7 |Number of nets: 7
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__buf_1 |Circuit 2: sky130_fd_sc_hd__buf_1
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-------------------------------------------|-------------------------------------------
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VGND |VGND
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X |X
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VNB |VNB
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A |A
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VPWR |VPWR
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VPB |VPB
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__buf_1 and sky130_fd_sc_hd__buf_1 are equivalent.
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Class sky130_fd_sc_hd__clkbuf_2 (0): Merged 2 parallel devices.
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Class sky130_fd_sc_hd__clkbuf_2 (1): Merged 2 parallel devices.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
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sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
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Number of devices: 4 |Number of devices: 4
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Number of nets: 7 |Number of nets: 7
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__clkbuf_2 |Circuit 2: sky130_fd_sc_hd__clkbuf_2
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-------------------------------------------|-------------------------------------------
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A |A
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VPWR |VPWR
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VPB |VPB
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VGND |VGND
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VNB |VNB
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X |X
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__clkbuf_2 and sky130_fd_sc_hd__clkbuf_2 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (1) |sky130_fd_pr__pfet_01v8_hvt (1)
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sky130_fd_pr__nfet_01v8 (1) |sky130_fd_pr__nfet_01v8 (1)
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Number of devices: 2 |Number of devices: 2
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Number of nets: 4 |Number of nets: 4
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__decap_4 |Circuit 2: sky130_fd_sc_hd__decap_4
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-------------------------------------------|-------------------------------------------
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VPB |VPB
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VNB |VNB
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VPWR |VPWR
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VGND |VGND
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__decap_4 and sky130_fd_sc_hd__decap_4 are equivalent.
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Class sky130_fd_sc_hd__buf_8 (0): Merged 18 parallel devices.
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Class sky130_fd_sc_hd__buf_8 (1): Merged 18 parallel devices.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (11->2) |sky130_fd_pr__nfet_01v8 (11->2)
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sky130_fd_pr__pfet_01v8_hvt (11->2) |sky130_fd_pr__pfet_01v8_hvt (11->2)
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Number of devices: 4 |Number of devices: 4
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Number of nets: 7 |Number of nets: 7
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__buf_8 |Circuit 2: sky130_fd_sc_hd__buf_8
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-------------------------------------------|-------------------------------------------
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X |X
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VGND |VGND
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VNB |VNB
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VPWR |VPWR
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VPB |VPB
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A |A
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__buf_8 and sky130_fd_sc_hd__buf_8 are equivalent.
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Class sky130_fd_sc_hd__dfbbn_2 (0): Merged 4 parallel devices.
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Class sky130_fd_sc_hd__dfbbn_2 (1): Merged 4 parallel devices.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__dfbbn_2 |Circuit 2: sky130_fd_sc_hd__dfbbn_2
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (22->20) |sky130_fd_pr__nfet_01v8 (22->20)
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sky130_fd_pr__pfet_01v8_hvt (22->20) |sky130_fd_pr__pfet_01v8_hvt (22->20)
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Number of devices: 40 |Number of devices: 40
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Number of nets: 29 |Number of nets: 29
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__dfbbn_2 |Circuit 2: sky130_fd_sc_hd__dfbbn_2
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-------------------------------------------|-------------------------------------------
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VPWR |VPWR
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RESET_B |RESET_B
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Q_N |Q_N
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Q |Q
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D |D
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CLK_N |CLK_N
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VPB |VPB
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VNB |VNB
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VGND |VGND
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SET_B |SET_B
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__dfbbn_2 and sky130_fd_sc_hd__dfbbn_2 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__dfrtp_1 |Circuit 2: sky130_fd_sc_hd__dfrtp_1
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__nfet_01v8 (14) |sky130_fd_pr__nfet_01v8 (14)
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sky130_fd_pr__pfet_01v8_hvt (14) |sky130_fd_pr__pfet_01v8_hvt (14)
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Number of devices: 28 |Number of devices: 28
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Number of nets: 21 |Number of nets: 21
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__dfrtp_1 |Circuit 2: sky130_fd_sc_hd__dfrtp_1
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-------------------------------------------|-------------------------------------------
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VPWR |VPWR
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RESET_B |RESET_B
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VPB |VPB
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VNB |VNB
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VGND |VGND
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D |D
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Q |Q
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CLK |CLK
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__dfrtp_1 and sky130_fd_sc_hd__dfrtp_1 are equivalent.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (2) |sky130_fd_pr__pfet_01v8_hvt (2)
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sky130_fd_pr__nfet_01v8 (2) |sky130_fd_pr__nfet_01v8 (2)
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Number of devices: 4 |Number of devices: 4
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Number of nets: 7 |Number of nets: 7
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__clkbuf_1 |Circuit 2: sky130_fd_sc_hd__clkbuf_1
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-------------------------------------------|-------------------------------------------
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VGND |VGND
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A |A
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VNB |VNB
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X |X
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VPWR |VPWR
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VPB |VPB
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__clkbuf_1 and sky130_fd_sc_hd__clkbuf_1 are equivalent.
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Class sky130_fd_sc_hd__buf_4 (0): Merged 6 parallel devices.
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Class sky130_fd_sc_hd__buf_4 (1): Merged 6 parallel devices.
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Subcircuit summary:
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Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
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-------------------------------------------|-------------------------------------------
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sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
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sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
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Number of devices: 4 |Number of devices: 4
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Number of nets: 7 |Number of nets: 7
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---------------------------------------------------------------------------------------
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Netlists match uniquely.
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Subcircuit pins:
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Circuit 1: sky130_fd_sc_hd__buf_4 |Circuit 2: sky130_fd_sc_hd__buf_4
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-------------------------------------------|-------------------------------------------
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X |X
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VGND |VGND
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VNB |VNB
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VPWR |VPWR
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VPB |VPB
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A |A
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---------------------------------------------------------------------------------------
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Cell pin lists are equivalent.
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Device classes sky130_fd_sc_hd__buf_4 and sky130_fd_sc_hd__buf_4 are equivalent.
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Class sky130_fd_sc_hd__clkbuf_16 (0): Merged 36 parallel devices.
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Class sky130_fd_sc_hd__clkbuf_16 (1): Merged 36 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (20->2) |sky130_fd_pr__pfet_01v8_hvt (20->2)
|
|
sky130_fd_pr__nfet_01v8 (20->2) |sky130_fd_pr__nfet_01v8 (20->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_16 |Circuit 2: sky130_fd_sc_hd__clkbuf_16
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
X |X
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkbuf_16 and sky130_fd_sc_hd__clkbuf_16 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2b_2 (0): Merged 4 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2b_2 (1): Merged 4 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (5->3) |sky130_fd_pr__pfet_01v8_hvt (5->3)
|
|
sky130_fd_pr__nfet_01v8 (5->3) |sky130_fd_pr__nfet_01v8 (5->3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2b_2 |Circuit 2: sky130_fd_sc_hd__nand2b_2
|
|
-------------------------------------------|-------------------------------------------
|
|
B |B
|
|
VGND |VGND
|
|
A_N |A_N
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
Y |Y
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2b_2 and sky130_fd_sc_hd__nand2b_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (2->1) |sky130_fd_pr__pfet_01v8_hvt (2->1)
|
|
sky130_fd_pr__nfet_01v8 (2->1) |sky130_fd_pr__nfet_01v8 (2->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_2 |Circuit 2: sky130_fd_sc_hd__inv_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
Y |Y
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_2 and sky130_fd_sc_hd__inv_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and2_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__and2_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->3) |sky130_fd_pr__pfet_01v8_hvt (4->3)
|
|
sky130_fd_pr__nfet_01v8 (4->3) |sky130_fd_pr__nfet_01v8 (4->3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2_2 |Circuit 2: sky130_fd_sc_hd__and2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
X |X
|
|
A |A
|
|
B |B
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2_2 and sky130_fd_sc_hd__and2_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkbuf_8 (0): Merged 16 parallel devices.
|
|
Class sky130_fd_sc_hd__clkbuf_8 (1): Merged 16 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (10->2) |sky130_fd_pr__pfet_01v8_hvt (10->2)
|
|
sky130_fd_pr__nfet_01v8 (10->2) |sky130_fd_pr__nfet_01v8 (10->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_8 |Circuit 2: sky130_fd_sc_hd__clkbuf_8
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkbuf_8 and sky130_fd_sc_hd__clkbuf_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkbuf_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__clkbuf_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (5->2) |sky130_fd_pr__pfet_01v8_hvt (5->2)
|
|
sky130_fd_pr__nfet_01v8 (5->2) |sky130_fd_pr__nfet_01v8 (5->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkbuf_4 |Circuit 2: sky130_fd_sc_hd__clkbuf_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
X |X
|
|
VPB |VPB
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkbuf_4 and sky130_fd_sc_hd__clkbuf_4 are equivalent.
|
|
|
|
Circuit 2 cell gpio_logic_high is a black box; will not flatten Circuit 1
|
|
Class gpio_logic_high (0): Merged 35 parallel devices.
|
|
Warning: Equate pins: cell gpio_logic_high is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: gpio_logic_high |Circuit 2: gpio_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
gpio_logic1 |gpio_logic1
|
|
vccd1 |vccd1
|
|
vssd1 |vssd1
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes gpio_logic_high and gpio_logic_high are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->1) |sky130_fd_pr__pfet_01v8_hvt (4->1)
|
|
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_4 |Circuit 2: sky130_fd_sc_hd__inv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
Y |Y
|
|
A |A
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_4 and sky130_fd_sc_hd__inv_4 are equivalent.
|
|
|
|
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VPB
|
|
Cell sky130_fd_sc_hd__conb_1 (0) disconnected node: VNB
|
|
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VNB
|
|
Cell sky130_fd_sc_hd__conb_1 (1) disconnected node: VPB
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__res_generic_po (2) |sky130_fd_pr__res_generic_po (2)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 4 |Number of nets: 4
|
|
---------------------------------------------------------------------------------------
|
|
Resolving symmetries by property value.
|
|
Resolving symmetries by pin name.
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__conb_1 |Circuit 2: sky130_fd_sc_hd__conb_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
LO |LO
|
|
HI |HI
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__conb_1 and sky130_fd_sc_hd__conb_1 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (3) |sky130_fd_pr__pfet_01v8_hvt (3)
|
|
sky130_fd_pr__nfet_01v8 (3) |sky130_fd_pr__nfet_01v8 (3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2_1 |Circuit 2: sky130_fd_sc_hd__and2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
X |X
|
|
A |A
|
|
B |B
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2_1 and sky130_fd_sc_hd__and2_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_6 (0): Merged 12 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_6 (1): Merged 12 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
|
|
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_6 |Circuit 2: sky130_fd_sc_hd__buf_6
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
X |X
|
|
VNB |VNB
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_6 and sky130_fd_sc_hd__buf_6 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_12 (0): Merged 28 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_12 (1): Merged 28 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_12 |Circuit 2: sky130_fd_sc_hd__buf_12
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_12 and sky130_fd_sc_hd__buf_12 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkinv_4 (0): Merged 8 parallel devices.
|
|
Class sky130_fd_sc_hd__clkinv_4 (1): Merged 8 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
|
|
sky130_fd_pr__nfet_01v8 (4->1) |sky130_fd_pr__nfet_01v8 (4->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_4 |Circuit 2: sky130_fd_sc_hd__clkinv_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
Y |Y
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkinv_4 and sky130_fd_sc_hd__clkinv_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__mux2_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__mux2_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (9->6) |sky130_fd_pr__pfet_01v8_hvt (9->6)
|
|
sky130_fd_pr__nfet_01v8 (9->6) |sky130_fd_pr__nfet_01v8 (9->6)
|
|
Number of devices: 12 |Number of devices: 12
|
|
Number of nets: 14 |Number of nets: 14
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_4 |Circuit 2: sky130_fd_sc_hd__mux2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
VPWR |VPWR
|
|
S |S
|
|
VNB |VNB
|
|
VPB |VPB
|
|
X |X
|
|
A0 |A0
|
|
A1 |A1
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__mux2_4 and sky130_fd_sc_hd__mux2_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_4 (0): Merged 12 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_4 (1): Merged 12 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->2) |sky130_fd_pr__nfet_01v8 (8->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (8->2) |sky130_fd_pr__pfet_01v8_hvt (8->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_4 |Circuit 2: sky130_fd_sc_hd__nand2_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
Y |Y
|
|
A |A
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
B |B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_4 and sky130_fd_sc_hd__nand2_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__clkinv_8 (0): Merged 18 parallel devices.
|
|
Class sky130_fd_sc_hd__clkinv_8 (1): Merged 18 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->1) |sky130_fd_pr__nfet_01v8 (8->1)
|
|
sky130_fd_pr__pfet_01v8_hvt (12->1) |sky130_fd_pr__pfet_01v8_hvt (12->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__clkinv_8 |Circuit 2: sky130_fd_sc_hd__clkinv_8
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
Y |Y
|
|
A |A
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__clkinv_8 and sky130_fd_sc_hd__clkinv_8 are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
|
|
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
|
|
Number of devices: 12 |Number of devices: 12
|
|
Number of nets: 14 |Number of nets: 14
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_1 |Circuit 2: sky130_fd_sc_hd__mux2_1
|
|
-------------------------------------------|-------------------------------------------
|
|
VPB |VPB
|
|
VNB |VNB
|
|
A0 |A0
|
|
A1 |A1
|
|
X |X
|
|
VPWR |VPWR
|
|
S |S
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__mux2_1 and sky130_fd_sc_hd__mux2_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__buf_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__buf_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (3->2) |sky130_fd_pr__pfet_01v8_hvt (3->2)
|
|
sky130_fd_pr__nfet_01v8 (3->2) |sky130_fd_pr__nfet_01v8 (3->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 7 |Number of nets: 7
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__buf_2 |Circuit 2: sky130_fd_sc_hd__buf_2
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__buf_2 and sky130_fd_sc_hd__buf_2 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and3b_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__and3b_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (8->5) |sky130_fd_pr__nfet_01v8 (8->5)
|
|
sky130_fd_pr__pfet_01v8_hvt (8->5) |sky130_fd_pr__pfet_01v8_hvt (8->5)
|
|
Number of devices: 10 |Number of devices: 10
|
|
Number of nets: 12 |Number of nets: 12
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and3b_4 |Circuit 2: sky130_fd_sc_hd__and3b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
X |X
|
|
C |C
|
|
B |B
|
|
A_N |A_N
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and3b_4 and sky130_fd_sc_hd__and3b_4 are equivalent.
|
|
|
|
Circuit 2 cell gpio_defaults_block is a black box; will not flatten Circuit 1
|
|
Class gpio_defaults_block (0): Merged 27 parallel devices.
|
|
Warning: Equate pins: cell gpio_defaults_block is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: gpio_defaults_block |Circuit 2: gpio_defaults_block
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
gpio_defaults[3] |gpio_defaults[3]
|
|
gpio_defaults[5] |gpio_defaults[5]
|
|
gpio_defaults[7] |gpio_defaults[7]
|
|
gpio_defaults[9] |gpio_defaults[9]
|
|
gpio_defaults[0] |gpio_defaults[0]
|
|
gpio_defaults[2] |gpio_defaults[2]
|
|
gpio_defaults[4] |gpio_defaults[4]
|
|
gpio_defaults[11] |gpio_defaults[11]
|
|
gpio_defaults[6] |gpio_defaults[6]
|
|
gpio_defaults[10] |gpio_defaults[10]
|
|
gpio_defaults[12] |gpio_defaults[12]
|
|
gpio_defaults[8] |gpio_defaults[8]
|
|
gpio_defaults[1] |gpio_defaults[1]
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes gpio_defaults_block and gpio_defaults_block are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_8 (0): Merged 28 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_8 (1): Merged 28 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (16->2) |sky130_fd_pr__nfet_01v8 (16->2)
|
|
sky130_fd_pr__pfet_01v8_hvt (16->2) |sky130_fd_pr__pfet_01v8_hvt (16->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_8 |Circuit 2: sky130_fd_sc_hd__nand2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
Y |Y
|
|
VGND |VGND
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
B |B
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_8 and sky130_fd_sc_hd__nand2_8 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__dfrtp_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__dfrtp_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__dfrtp_2 |Circuit 2: sky130_fd_sc_hd__dfrtp_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (15->14) |sky130_fd_pr__nfet_01v8 (15->14)
|
|
sky130_fd_pr__pfet_01v8_hvt (15->14) |sky130_fd_pr__pfet_01v8_hvt (15->14)
|
|
Number of devices: 28 |Number of devices: 28
|
|
Number of nets: 21 |Number of nets: 21
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__dfrtp_2 |Circuit 2: sky130_fd_sc_hd__dfrtp_2
|
|
-------------------------------------------|-------------------------------------------
|
|
RESET_B |RESET_B
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VGND |VGND
|
|
Q |Q
|
|
D |D
|
|
CLK |CLK
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__dfrtp_2 and sky130_fd_sc_hd__dfrtp_2 are equivalent.
|
|
|
|
Circuit 2 cell digital_locked_loop is a black box; will not flatten Circuit 1
|
|
Class digital_locked_loop (0): Merged 314 parallel devices.
|
|
Warning: Equate pins: cell digital_locked_loop is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: digital_locked_loop |Circuit 2: digital_locked_loop
|
|
-------------------------------------------|-------------------------------------------
|
|
ext_trim[10] |ext_trim[10]
|
|
ext_trim[11] |ext_trim[11]
|
|
ext_trim[12] |ext_trim[12]
|
|
ext_trim[13] |ext_trim[13]
|
|
ext_trim[14] |ext_trim[14]
|
|
ext_trim[15] |ext_trim[15]
|
|
ext_trim[16] |ext_trim[16]
|
|
ext_trim[17] |ext_trim[17]
|
|
ext_trim[18] |ext_trim[18]
|
|
ext_trim[19] |ext_trim[19]
|
|
ext_trim[7] |ext_trim[7]
|
|
ext_trim[8] |ext_trim[8]
|
|
ext_trim[9] |ext_trim[9]
|
|
osc |osc
|
|
resetb |resetb
|
|
clockp[0] |clockp[0]
|
|
clockp[1] |clockp[1]
|
|
dco |dco
|
|
div[0] |div[0]
|
|
div[1] |div[1]
|
|
div[2] |div[2]
|
|
div[3] |div[3]
|
|
div[4] |div[4]
|
|
enable |enable
|
|
ext_trim[0] |ext_trim[0]
|
|
ext_trim[1] |ext_trim[1]
|
|
ext_trim[20] |ext_trim[20]
|
|
ext_trim[21] |ext_trim[21]
|
|
ext_trim[22] |ext_trim[22]
|
|
ext_trim[23] |ext_trim[23]
|
|
ext_trim[24] |ext_trim[24]
|
|
ext_trim[25] |ext_trim[25]
|
|
ext_trim[2] |ext_trim[2]
|
|
ext_trim[3] |ext_trim[3]
|
|
ext_trim[4] |ext_trim[4]
|
|
ext_trim[5] |ext_trim[5]
|
|
ext_trim[6] |ext_trim[6]
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes digital_locked_loop and digital_locked_loop are equivalent.
|
|
|
|
Circuit 2 cell mgmt_core_wrapper is a black box; will not flatten Circuit 1
|
|
Class mgmt_core_wrapper (0): Merged 67091 parallel devices.
|
|
Warning: Equate pins: cell mgmt_core_wrapper is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mgmt_core_wrapper |Circuit 2: mgmt_core_wrapper
|
|
-------------------------------------------|-------------------------------------------
|
|
la_output[77] |la_output[77]
|
|
irq[1] |irq[1]
|
|
irq[2] |irq[2]
|
|
irq[0] |irq[0]
|
|
mprj_adr_o[10] |mprj_adr_o[10]
|
|
mprj_adr_o[11] |mprj_adr_o[11]
|
|
mprj_adr_o[12] |mprj_adr_o[12]
|
|
mprj_adr_o[13] |mprj_adr_o[13]
|
|
mprj_adr_o[14] |mprj_adr_o[14]
|
|
mprj_adr_o[15] |mprj_adr_o[15]
|
|
mprj_adr_o[16] |mprj_adr_o[16]
|
|
mprj_adr_o[17] |mprj_adr_o[17]
|
|
mprj_adr_o[18] |mprj_adr_o[18]
|
|
mprj_adr_o[19] |mprj_adr_o[19]
|
|
mprj_adr_o[20] |mprj_adr_o[20]
|
|
mprj_adr_o[21] |mprj_adr_o[21]
|
|
mprj_adr_o[22] |mprj_adr_o[22]
|
|
mprj_adr_o[23] |mprj_adr_o[23]
|
|
mprj_adr_o[24] |mprj_adr_o[24]
|
|
mprj_adr_o[25] |mprj_adr_o[25]
|
|
mprj_adr_o[26] |mprj_adr_o[26]
|
|
mprj_adr_o[27] |mprj_adr_o[27]
|
|
mprj_adr_o[28] |mprj_adr_o[28]
|
|
mprj_adr_o[29] |mprj_adr_o[29]
|
|
mprj_adr_o[30] |mprj_adr_o[30]
|
|
mprj_adr_o[31] |mprj_adr_o[31]
|
|
mprj_adr_o[8] |mprj_adr_o[8]
|
|
mprj_adr_o[9] |mprj_adr_o[9]
|
|
mprj_dat_i[10] |mprj_dat_i[10]
|
|
mprj_dat_i[11] |mprj_dat_i[11]
|
|
mprj_dat_i[12] |mprj_dat_i[12]
|
|
mprj_dat_i[13] |mprj_dat_i[13]
|
|
mprj_dat_i[14] |mprj_dat_i[14]
|
|
mprj_dat_i[15] |mprj_dat_i[15]
|
|
mprj_dat_i[16] |mprj_dat_i[16]
|
|
mprj_dat_i[17] |mprj_dat_i[17]
|
|
mprj_dat_i[18] |mprj_dat_i[18]
|
|
mprj_dat_i[19] |mprj_dat_i[19]
|
|
mprj_dat_i[20] |mprj_dat_i[20]
|
|
mprj_dat_i[21] |mprj_dat_i[21]
|
|
mprj_dat_i[22] |mprj_dat_i[22]
|
|
mprj_dat_i[23] |mprj_dat_i[23]
|
|
mprj_dat_i[24] |mprj_dat_i[24]
|
|
mprj_dat_i[25] |mprj_dat_i[25]
|
|
mprj_dat_i[26] |mprj_dat_i[26]
|
|
mprj_dat_i[27] |mprj_dat_i[27]
|
|
mprj_dat_i[28] |mprj_dat_i[28]
|
|
mprj_dat_i[29] |mprj_dat_i[29]
|
|
mprj_dat_i[30] |mprj_dat_i[30]
|
|
mprj_dat_i[31] |mprj_dat_i[31]
|
|
mprj_dat_i[8] |mprj_dat_i[8]
|
|
mprj_dat_i[9] |mprj_dat_i[9]
|
|
mprj_dat_o[10] |mprj_dat_o[10]
|
|
mprj_dat_o[11] |mprj_dat_o[11]
|
|
mprj_dat_o[12] |mprj_dat_o[12]
|
|
mprj_dat_o[13] |mprj_dat_o[13]
|
|
mprj_dat_o[14] |mprj_dat_o[14]
|
|
mprj_dat_o[15] |mprj_dat_o[15]
|
|
mprj_dat_o[16] |mprj_dat_o[16]
|
|
mprj_dat_o[17] |mprj_dat_o[17]
|
|
mprj_dat_o[18] |mprj_dat_o[18]
|
|
mprj_dat_o[19] |mprj_dat_o[19]
|
|
mprj_dat_o[20] |mprj_dat_o[20]
|
|
mprj_dat_o[21] |mprj_dat_o[21]
|
|
mprj_dat_o[22] |mprj_dat_o[22]
|
|
mprj_dat_o[23] |mprj_dat_o[23]
|
|
mprj_dat_o[24] |mprj_dat_o[24]
|
|
mprj_dat_o[25] |mprj_dat_o[25]
|
|
mprj_dat_o[26] |mprj_dat_o[26]
|
|
mprj_dat_o[27] |mprj_dat_o[27]
|
|
mprj_dat_o[28] |mprj_dat_o[28]
|
|
mprj_dat_o[29] |mprj_dat_o[29]
|
|
mprj_dat_o[30] |mprj_dat_o[30]
|
|
mprj_dat_o[31] |mprj_dat_o[31]
|
|
mprj_dat_o[8] |mprj_dat_o[8]
|
|
mprj_dat_o[9] |mprj_dat_o[9]
|
|
user_irq_ena[0] |user_irq_ena[0]
|
|
user_irq_ena[1] |user_irq_ena[1]
|
|
user_irq_ena[2] |user_irq_ena[2]
|
|
mprj_adr_o[7] |mprj_adr_o[7]
|
|
la_oenb[118] |la_oenb[118]
|
|
la_oenb[119] |la_oenb[119]
|
|
mprj_cyc_o |mprj_cyc_o
|
|
mprj_dat_i[0] |mprj_dat_i[0]
|
|
la_oenb[120] |la_oenb[120]
|
|
la_oenb[121] |la_oenb[121]
|
|
la_oenb[122] |la_oenb[122]
|
|
la_oenb[123] |la_oenb[123]
|
|
la_oenb[124] |la_oenb[124]
|
|
la_oenb[125] |la_oenb[125]
|
|
la_oenb[126] |la_oenb[126]
|
|
la_oenb[127] |la_oenb[127]
|
|
la_output[116] |la_output[116]
|
|
la_output[117] |la_output[117]
|
|
mprj_dat_i[1] |mprj_dat_i[1]
|
|
la_output[118] |la_output[118]
|
|
la_output[119] |la_output[119]
|
|
la_output[120] |la_output[120]
|
|
la_output[121] |la_output[121]
|
|
la_output[122] |la_output[122]
|
|
la_output[123] |la_output[123]
|
|
la_output[124] |la_output[124]
|
|
la_output[125] |la_output[125]
|
|
la_output[126] |la_output[126]
|
|
la_output[127] |la_output[127]
|
|
mprj_dat_i[2] |mprj_dat_i[2]
|
|
la_iena[117] |la_iena[117]
|
|
mprj_ack_i |mprj_ack_i
|
|
mprj_dat_i[3] |mprj_dat_i[3]
|
|
mprj_dat_i[4] |mprj_dat_i[4]
|
|
mprj_dat_i[5] |mprj_dat_i[5]
|
|
mprj_dat_i[6] |mprj_dat_i[6]
|
|
mprj_dat_i[7] |mprj_dat_i[7]
|
|
mprj_adr_o[0] |mprj_adr_o[0]
|
|
la_iena[118] |la_iena[118]
|
|
mprj_dat_o[0] |mprj_dat_o[0]
|
|
la_iena[119] |la_iena[119]
|
|
la_iena[120] |la_iena[120]
|
|
la_iena[121] |la_iena[121]
|
|
la_iena[122] |la_iena[122]
|
|
la_iena[123] |la_iena[123]
|
|
la_iena[124] |la_iena[124]
|
|
la_iena[125] |la_iena[125]
|
|
la_iena[126] |la_iena[126]
|
|
la_iena[127] |la_iena[127]
|
|
mprj_adr_o[1] |mprj_adr_o[1]
|
|
mprj_dat_o[1] |mprj_dat_o[1]
|
|
la_input[117] |la_input[117]
|
|
la_input[118] |la_input[118]
|
|
la_input[119] |la_input[119]
|
|
la_input[120] |la_input[120]
|
|
la_input[121] |la_input[121]
|
|
la_input[122] |la_input[122]
|
|
la_input[123] |la_input[123]
|
|
la_input[124] |la_input[124]
|
|
la_input[125] |la_input[125]
|
|
la_input[126] |la_input[126]
|
|
mprj_dat_o[2] |mprj_dat_o[2]
|
|
mprj_adr_o[2] |mprj_adr_o[2]
|
|
la_input[127] |la_input[127]
|
|
mprj_dat_o[3] |mprj_dat_o[3]
|
|
mprj_dat_o[4] |mprj_dat_o[4]
|
|
mprj_dat_o[5] |mprj_dat_o[5]
|
|
mprj_dat_o[6] |mprj_dat_o[6]
|
|
mprj_dat_o[7] |mprj_dat_o[7]
|
|
la_oenb[117] |la_oenb[117]
|
|
mprj_adr_o[3] |mprj_adr_o[3]
|
|
mprj_sel_o[0] |mprj_sel_o[0]
|
|
mprj_sel_o[1] |mprj_sel_o[1]
|
|
mprj_sel_o[2] |mprj_sel_o[2]
|
|
mprj_sel_o[3] |mprj_sel_o[3]
|
|
mprj_stb_o |mprj_stb_o
|
|
mprj_wb_iena |mprj_wb_iena
|
|
mprj_we_o |mprj_we_o
|
|
mprj_adr_o[4] |mprj_adr_o[4]
|
|
mprj_adr_o[5] |mprj_adr_o[5]
|
|
mprj_adr_o[6] |mprj_adr_o[6]
|
|
la_output[104] |la_output[104]
|
|
la_output[105] |la_output[105]
|
|
la_output[106] |la_output[106]
|
|
la_output[107] |la_output[107]
|
|
la_output[108] |la_output[108]
|
|
la_output[109] |la_output[109]
|
|
la_output[110] |la_output[110]
|
|
la_output[111] |la_output[111]
|
|
la_output[112] |la_output[112]
|
|
la_output[113] |la_output[113]
|
|
la_output[114] |la_output[114]
|
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la_output[115] |la_output[115]
|
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la_output[97] |la_output[97]
|
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la_output[98] |la_output[98]
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la_output[99] |la_output[99]
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la_iena[98] |la_iena[98]
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la_iena[99] |la_iena[99]
|
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la_input[100] |la_input[100]
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la_input[101] |la_input[101]
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la_input[102] |la_input[102]
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la_input[103] |la_input[103]
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la_input[104] |la_input[104]
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la_input[105] |la_input[105]
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la_input[106] |la_input[106]
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la_input[107] |la_input[107]
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la_input[108] |la_input[108]
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la_input[109] |la_input[109]
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la_input[110] |la_input[110]
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la_input[111] |la_input[111]
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la_input[112] |la_input[112]
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la_input[113] |la_input[113]
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la_input[114] |la_input[114]
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la_input[115] |la_input[115]
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la_input[116] |la_input[116]
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la_iena[111] |la_iena[111]
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la_iena[112] |la_iena[112]
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la_iena[113] |la_iena[113]
|
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la_iena[114] |la_iena[114]
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la_iena[115] |la_iena[115]
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la_iena[116] |la_iena[116]
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la_iena[100] |la_iena[100]
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la_iena[101] |la_iena[101]
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la_iena[102] |la_iena[102]
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la_iena[103] |la_iena[103]
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la_iena[104] |la_iena[104]
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la_input[97] |la_input[97]
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la_input[98] |la_input[98]
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la_input[99] |la_input[99]
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la_oenb[100] |la_oenb[100]
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la_oenb[101] |la_oenb[101]
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la_oenb[102] |la_oenb[102]
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la_oenb[103] |la_oenb[103]
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la_oenb[104] |la_oenb[104]
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la_oenb[105] |la_oenb[105]
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la_oenb[106] |la_oenb[106]
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la_oenb[107] |la_oenb[107]
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la_oenb[108] |la_oenb[108]
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la_oenb[109] |la_oenb[109]
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la_oenb[110] |la_oenb[110]
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la_oenb[111] |la_oenb[111]
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la_oenb[112] |la_oenb[112]
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la_oenb[113] |la_oenb[113]
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la_oenb[114] |la_oenb[114]
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la_oenb[115] |la_oenb[115]
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la_oenb[116] |la_oenb[116]
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la_iena[105] |la_iena[105]
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la_iena[106] |la_iena[106]
|
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la_iena[107] |la_iena[107]
|
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la_iena[108] |la_iena[108]
|
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la_iena[109] |la_iena[109]
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la_iena[110] |la_iena[110]
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la_oenb[97] |la_oenb[97]
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la_oenb[98] |la_oenb[98]
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la_oenb[99] |la_oenb[99]
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la_output[100] |la_output[100]
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la_output[101] |la_output[101]
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la_output[102] |la_output[102]
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la_output[103] |la_output[103]
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la_iena[83] |la_iena[83]
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la_input[78] |la_input[78]
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la_input[79] |la_input[79]
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la_input[80] |la_input[80]
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la_input[81] |la_input[81]
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la_input[82] |la_input[82]
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la_input[83] |la_input[83]
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la_input[84] |la_input[84]
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la_input[85] |la_input[85]
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la_input[86] |la_input[86]
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la_input[87] |la_input[87]
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la_input[88] |la_input[88]
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la_input[89] |la_input[89]
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la_input[90] |la_input[90]
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la_input[91] |la_input[91]
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la_input[92] |la_input[92]
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la_input[93] |la_input[93]
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la_input[94] |la_input[94]
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la_input[95] |la_input[95]
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la_input[96] |la_input[96]
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la_iena[84] |la_iena[84]
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la_iena[85] |la_iena[85]
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la_iena[96] |la_iena[96]
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la_iena[97] |la_iena[97]
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la_iena[86] |la_iena[86]
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la_iena[87] |la_iena[87]
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la_iena[88] |la_iena[88]
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la_iena[89] |la_iena[89]
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la_iena[90] |la_iena[90]
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la_iena[91] |la_iena[91]
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la_iena[92] |la_iena[92]
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la_iena[93] |la_iena[93]
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la_iena[94] |la_iena[94]
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la_iena[95] |la_iena[95]
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la_output[78] |la_output[78]
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la_output[79] |la_output[79]
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la_output[80] |la_output[80]
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la_output[81] |la_output[81]
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la_output[82] |la_output[82]
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la_output[83] |la_output[83]
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la_output[84] |la_output[84]
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la_output[85] |la_output[85]
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la_output[86] |la_output[86]
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la_output[87] |la_output[87]
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la_output[88] |la_output[88]
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la_output[89] |la_output[89]
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la_iena[78] |la_iena[78]
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la_iena[79] |la_iena[79]
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la_iena[80] |la_iena[80]
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la_iena[81] |la_iena[81]
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la_iena[82] |la_iena[82]
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la_oenb[78] |la_oenb[78]
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la_oenb[79] |la_oenb[79]
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la_oenb[80] |la_oenb[80]
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la_oenb[81] |la_oenb[81]
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la_oenb[82] |la_oenb[82]
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la_oenb[83] |la_oenb[83]
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la_oenb[84] |la_oenb[84]
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la_oenb[85] |la_oenb[85]
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la_oenb[86] |la_oenb[86]
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la_oenb[87] |la_oenb[87]
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la_oenb[88] |la_oenb[88]
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la_oenb[89] |la_oenb[89]
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la_oenb[90] |la_oenb[90]
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la_oenb[91] |la_oenb[91]
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la_oenb[92] |la_oenb[92]
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la_oenb[93] |la_oenb[93]
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la_oenb[94] |la_oenb[94]
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la_oenb[95] |la_oenb[95]
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la_oenb[96] |la_oenb[96]
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la_output[90] |la_output[90]
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la_output[91] |la_output[91]
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la_output[92] |la_output[92]
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la_output[93] |la_output[93]
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la_output[94] |la_output[94]
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la_output[95] |la_output[95]
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la_output[96] |la_output[96]
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la_oenb[58] |la_oenb[58]
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la_oenb[59] |la_oenb[59]
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la_oenb[60] |la_oenb[60]
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la_oenb[61] |la_oenb[61]
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la_oenb[62] |la_oenb[62]
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la_oenb[63] |la_oenb[63]
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la_oenb[64] |la_oenb[64]
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la_oenb[65] |la_oenb[65]
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la_oenb[66] |la_oenb[66]
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la_oenb[67] |la_oenb[67]
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la_oenb[68] |la_oenb[68]
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la_oenb[69] |la_oenb[69]
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la_oenb[70] |la_oenb[70]
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la_oenb[71] |la_oenb[71]
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la_oenb[72] |la_oenb[72]
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la_oenb[73] |la_oenb[73]
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la_oenb[74] |la_oenb[74]
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la_oenb[75] |la_oenb[75]
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la_oenb[76] |la_oenb[76]
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la_oenb[77] |la_oenb[77]
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la_output[58] |la_output[58]
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la_output[59] |la_output[59]
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la_output[60] |la_output[60]
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la_output[61] |la_output[61]
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la_output[62] |la_output[62]
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la_output[63] |la_output[63]
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la_output[64] |la_output[64]
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la_output[65] |la_output[65]
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la_output[66] |la_output[66]
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la_output[67] |la_output[67]
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la_output[68] |la_output[68]
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la_output[69] |la_output[69]
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la_output[70] |la_output[70]
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la_output[71] |la_output[71]
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la_output[72] |la_output[72]
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la_output[73] |la_output[73]
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la_output[74] |la_output[74]
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la_output[75] |la_output[75]
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la_output[76] |la_output[76]
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la_input[59] |la_input[59]
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la_input[60] |la_input[60]
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la_input[61] |la_input[61]
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la_input[62] |la_input[62]
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la_input[63] |la_input[63]
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la_input[64] |la_input[64]
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la_input[65] |la_input[65]
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la_input[66] |la_input[66]
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la_input[67] |la_input[67]
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la_input[68] |la_input[68]
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la_input[69] |la_input[69]
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la_input[70] |la_input[70]
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la_input[71] |la_input[71]
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la_input[72] |la_input[72]
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la_input[73] |la_input[73]
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la_input[74] |la_input[74]
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la_input[75] |la_input[75]
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la_input[76] |la_input[76]
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la_input[77] |la_input[77]
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la_iena[59] |la_iena[59]
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la_iena[60] |la_iena[60]
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la_iena[61] |la_iena[61]
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la_iena[62] |la_iena[62]
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la_iena[63] |la_iena[63]
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la_iena[64] |la_iena[64]
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la_iena[65] |la_iena[65]
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la_iena[66] |la_iena[66]
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la_iena[67] |la_iena[67]
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la_iena[68] |la_iena[68]
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la_iena[69] |la_iena[69]
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la_iena[70] |la_iena[70]
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la_iena[71] |la_iena[71]
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la_iena[72] |la_iena[72]
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la_iena[73] |la_iena[73]
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la_iena[74] |la_iena[74]
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la_iena[75] |la_iena[75]
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la_iena[76] |la_iena[76]
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la_iena[77] |la_iena[77]
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la_oenb[43] |la_oenb[43]
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la_oenb[44] |la_oenb[44]
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la_oenb[45] |la_oenb[45]
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la_oenb[46] |la_oenb[46]
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la_oenb[47] |la_oenb[47]
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la_oenb[48] |la_oenb[48]
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la_oenb[49] |la_oenb[49]
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la_oenb[50] |la_oenb[50]
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la_oenb[51] |la_oenb[51]
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la_oenb[52] |la_oenb[52]
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la_oenb[53] |la_oenb[53]
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la_oenb[54] |la_oenb[54]
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la_oenb[55] |la_oenb[55]
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la_oenb[56] |la_oenb[56]
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la_oenb[57] |la_oenb[57]
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la_oenb[39] |la_oenb[39]
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la_input[39] |la_input[39]
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la_input[40] |la_input[40]
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la_input[41] |la_input[41]
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la_input[42] |la_input[42]
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la_input[43] |la_input[43]
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la_input[44] |la_input[44]
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la_input[45] |la_input[45]
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la_input[46] |la_input[46]
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la_input[47] |la_input[47]
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la_input[48] |la_input[48]
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la_input[49] |la_input[49]
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la_input[50] |la_input[50]
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la_input[51] |la_input[51]
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la_input[52] |la_input[52]
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la_input[53] |la_input[53]
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la_input[54] |la_input[54]
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la_input[55] |la_input[55]
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la_input[56] |la_input[56]
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la_input[57] |la_input[57]
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la_input[58] |la_input[58]
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la_iena[39] |la_iena[39]
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la_iena[40] |la_iena[40]
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la_iena[41] |la_iena[41]
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la_iena[42] |la_iena[42]
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la_iena[43] |la_iena[43]
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la_iena[44] |la_iena[44]
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la_iena[45] |la_iena[45]
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la_iena[46] |la_iena[46]
|
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la_iena[47] |la_iena[47]
|
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la_iena[48] |la_iena[48]
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la_iena[49] |la_iena[49]
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la_iena[50] |la_iena[50]
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la_iena[51] |la_iena[51]
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la_iena[52] |la_iena[52]
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la_iena[53] |la_iena[53]
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la_iena[54] |la_iena[54]
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la_output[39] |la_output[39]
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la_output[40] |la_output[40]
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la_output[41] |la_output[41]
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la_iena[55] |la_iena[55]
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la_iena[56] |la_iena[56]
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la_iena[57] |la_iena[57]
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la_iena[58] |la_iena[58]
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la_output[42] |la_output[42]
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la_output[43] |la_output[43]
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la_output[44] |la_output[44]
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la_output[45] |la_output[45]
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la_output[46] |la_output[46]
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la_output[47] |la_output[47]
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la_output[48] |la_output[48]
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la_output[49] |la_output[49]
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la_output[50] |la_output[50]
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la_output[51] |la_output[51]
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la_output[52] |la_output[52]
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la_output[53] |la_output[53]
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la_output[54] |la_output[54]
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la_output[55] |la_output[55]
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la_output[56] |la_output[56]
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la_output[57] |la_output[57]
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la_oenb[40] |la_oenb[40]
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la_oenb[41] |la_oenb[41]
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la_oenb[42] |la_oenb[42]
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la_oenb[33] |la_oenb[33]
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la_oenb[34] |la_oenb[34]
|
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la_iena[30] |la_iena[30]
|
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la_iena[31] |la_iena[31]
|
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la_input[30] |la_input[30]
|
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la_input[31] |la_input[31]
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la_input[32] |la_input[32]
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la_input[33] |la_input[33]
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la_input[34] |la_input[34]
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la_input[35] |la_input[35]
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la_input[36] |la_input[36]
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la_input[37] |la_input[37]
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la_input[38] |la_input[38]
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la_input[20] |la_input[20]
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la_input[21] |la_input[21]
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la_input[22] |la_input[22]
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la_input[23] |la_input[23]
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la_input[24] |la_input[24]
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la_input[25] |la_input[25]
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la_input[26] |la_input[26]
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la_input[27] |la_input[27]
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la_input[28] |la_input[28]
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la_input[29] |la_input[29]
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la_output[19] |la_output[19]
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la_output[20] |la_output[20]
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la_output[21] |la_output[21]
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la_output[22] |la_output[22]
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la_output[23] |la_output[23]
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la_output[24] |la_output[24]
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la_output[25] |la_output[25]
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la_output[26] |la_output[26]
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la_output[27] |la_output[27]
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la_output[28] |la_output[28]
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la_output[29] |la_output[29]
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la_output[30] |la_output[30]
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la_output[31] |la_output[31]
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la_output[32] |la_output[32]
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la_output[33] |la_output[33]
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la_output[34] |la_output[34]
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la_output[35] |la_output[35]
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la_output[36] |la_output[36]
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la_output[37] |la_output[37]
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la_output[38] |la_output[38]
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la_iena[32] |la_iena[32]
|
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la_iena[33] |la_iena[33]
|
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la_iena[34] |la_iena[34]
|
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la_iena[35] |la_iena[35]
|
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la_iena[36] |la_iena[36]
|
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la_iena[37] |la_iena[37]
|
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la_iena[38] |la_iena[38]
|
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la_oenb[35] |la_oenb[35]
|
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la_oenb[36] |la_oenb[36]
|
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la_oenb[37] |la_oenb[37]
|
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la_oenb[38] |la_oenb[38]
|
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la_oenb[32] |la_oenb[32]
|
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la_iena[20] |la_iena[20]
|
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la_iena[21] |la_iena[21]
|
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la_iena[22] |la_iena[22]
|
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la_iena[23] |la_iena[23]
|
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la_iena[24] |la_iena[24]
|
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la_iena[25] |la_iena[25]
|
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la_iena[26] |la_iena[26]
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la_iena[27] |la_iena[27]
|
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la_iena[28] |la_iena[28]
|
|
la_iena[29] |la_iena[29]
|
|
la_oenb[19] |la_oenb[19]
|
|
la_oenb[20] |la_oenb[20]
|
|
la_oenb[21] |la_oenb[21]
|
|
la_oenb[22] |la_oenb[22]
|
|
la_oenb[23] |la_oenb[23]
|
|
la_oenb[24] |la_oenb[24]
|
|
la_oenb[25] |la_oenb[25]
|
|
la_oenb[26] |la_oenb[26]
|
|
la_oenb[27] |la_oenb[27]
|
|
la_oenb[28] |la_oenb[28]
|
|
la_oenb[29] |la_oenb[29]
|
|
la_oenb[30] |la_oenb[30]
|
|
la_oenb[31] |la_oenb[31]
|
|
la_output[10] |la_output[10]
|
|
la_input[13] |la_input[13]
|
|
la_input[7] |la_input[7]
|
|
la_input[14] |la_input[14]
|
|
la_input[15] |la_input[15]
|
|
la_output[3] |la_output[3]
|
|
la_iena[5] |la_iena[5]
|
|
la_input[16] |la_input[16]
|
|
la_input[17] |la_input[17]
|
|
la_input[4] |la_input[4]
|
|
la_output[9] |la_output[9]
|
|
la_input[18] |la_input[18]
|
|
la_input[2] |la_input[2]
|
|
la_input[8] |la_input[8]
|
|
la_input[10] |la_input[10]
|
|
la_oenb[8] |la_oenb[8]
|
|
la_output[12] |la_output[12]
|
|
la_iena[3] |la_iena[3]
|
|
la_iena[6] |la_iena[6]
|
|
la_output[4] |la_output[4]
|
|
la_oenb[5] |la_oenb[5]
|
|
la_oenb[6] |la_oenb[6]
|
|
la_output[13] |la_output[13]
|
|
la_output[14] |la_output[14]
|
|
la_input[9] |la_input[9]
|
|
la_oenb[0] |la_oenb[0]
|
|
la_output[15] |la_output[15]
|
|
la_output[16] |la_output[16]
|
|
la_oenb[3] |la_oenb[3]
|
|
la_iena[11] |la_iena[11]
|
|
la_iena[0] |la_iena[0]
|
|
la_iena[7] |la_iena[7]
|
|
la_iena[10] |la_iena[10]
|
|
la_iena[12] |la_iena[12]
|
|
la_iena[13] |la_iena[13]
|
|
la_iena[14] |la_iena[14]
|
|
la_oenb[10] |la_oenb[10]
|
|
la_iena[15] |la_iena[15]
|
|
la_iena[16] |la_iena[16]
|
|
la_iena[17] |la_iena[17]
|
|
la_iena[18] |la_iena[18]
|
|
la_iena[19] |la_iena[19]
|
|
la_iena[1] |la_iena[1]
|
|
la_iena[8] |la_iena[8]
|
|
la_output[17] |la_output[17]
|
|
la_output[18] |la_output[18]
|
|
la_input[11] |la_input[11]
|
|
la_oenb[11] |la_oenb[11]
|
|
la_input[5] |la_input[5]
|
|
la_output[1] |la_output[1]
|
|
la_oenb[9] |la_oenb[9]
|
|
la_output[7] |la_output[7]
|
|
la_oenb[4] |la_oenb[4]
|
|
la_iena[4] |la_iena[4]
|
|
la_input[0] |la_input[0]
|
|
la_iena[9] |la_iena[9]
|
|
la_oenb[12] |la_oenb[12]
|
|
la_oenb[13] |la_oenb[13]
|
|
la_oenb[14] |la_oenb[14]
|
|
la_oenb[15] |la_oenb[15]
|
|
la_oenb[16] |la_oenb[16]
|
|
la_oenb[17] |la_oenb[17]
|
|
la_oenb[18] |la_oenb[18]
|
|
la_iena[2] |la_iena[2]
|
|
la_oenb[1] |la_oenb[1]
|
|
la_oenb[7] |la_oenb[7]
|
|
la_output[0] |la_output[0]
|
|
la_output[5] |la_output[5]
|
|
la_input[6] |la_input[6]
|
|
la_input[19] |la_input[19]
|
|
la_output[2] |la_output[2]
|
|
la_input[3] |la_input[3]
|
|
la_input[1] |la_input[1]
|
|
la_output[8] |la_output[8]
|
|
la_input[12] |la_input[12]
|
|
la_oenb[2] |la_oenb[2]
|
|
la_output[6] |la_output[6]
|
|
la_output[11] |la_output[11]
|
|
gpio_outenb_pad |gpio_outenb_pad
|
|
core_clk |core_clk
|
|
core_rstn |core_rstn
|
|
gpio_in_pad |gpio_in_pad
|
|
gpio_inenb_pad |gpio_inenb_pad
|
|
gpio_mode0_pad |gpio_mode0_pad
|
|
gpio_mode1_pad |gpio_mode1_pad
|
|
gpio_out_pad |gpio_out_pad
|
|
debug_in |debug_in
|
|
debug_mode |debug_mode
|
|
debug_oeb |debug_oeb
|
|
debug_out |debug_out
|
|
flash_clk |flash_clk
|
|
flash_csb |flash_csb
|
|
flash_io0_di |flash_io0_di
|
|
flash_io0_do |flash_io0_do
|
|
flash_io0_oeb |flash_io0_oeb
|
|
flash_io1_di |flash_io1_di
|
|
flash_io1_do |flash_io1_do
|
|
flash_io1_oeb |flash_io1_oeb
|
|
flash_io2_di |flash_io2_di
|
|
flash_io2_do |flash_io2_do
|
|
flash_io2_oeb |flash_io2_oeb
|
|
flash_io3_di |flash_io3_di
|
|
flash_io3_do |flash_io3_do
|
|
flash_io3_oeb |flash_io3_oeb
|
|
hk_ack_i |hk_ack_i
|
|
hk_cyc_o |hk_cyc_o
|
|
hk_dat_i[0] |hk_dat_i[0]
|
|
hk_dat_i[10] |hk_dat_i[10]
|
|
hk_dat_i[11] |hk_dat_i[11]
|
|
hk_dat_i[12] |hk_dat_i[12]
|
|
hk_dat_i[13] |hk_dat_i[13]
|
|
hk_dat_i[14] |hk_dat_i[14]
|
|
hk_dat_i[15] |hk_dat_i[15]
|
|
hk_dat_i[16] |hk_dat_i[16]
|
|
hk_dat_i[17] |hk_dat_i[17]
|
|
hk_dat_i[18] |hk_dat_i[18]
|
|
hk_dat_i[19] |hk_dat_i[19]
|
|
hk_dat_i[1] |hk_dat_i[1]
|
|
hk_dat_i[20] |hk_dat_i[20]
|
|
hk_dat_i[21] |hk_dat_i[21]
|
|
hk_dat_i[22] |hk_dat_i[22]
|
|
hk_dat_i[23] |hk_dat_i[23]
|
|
hk_dat_i[24] |hk_dat_i[24]
|
|
hk_dat_i[25] |hk_dat_i[25]
|
|
hk_dat_i[26] |hk_dat_i[26]
|
|
hk_dat_i[27] |hk_dat_i[27]
|
|
hk_dat_i[28] |hk_dat_i[28]
|
|
hk_dat_i[29] |hk_dat_i[29]
|
|
hk_dat_i[2] |hk_dat_i[2]
|
|
hk_dat_i[30] |hk_dat_i[30]
|
|
hk_dat_i[31] |hk_dat_i[31]
|
|
hk_dat_i[3] |hk_dat_i[3]
|
|
hk_dat_i[4] |hk_dat_i[4]
|
|
hk_dat_i[5] |hk_dat_i[5]
|
|
hk_dat_i[6] |hk_dat_i[6]
|
|
hk_dat_i[7] |hk_dat_i[7]
|
|
hk_dat_i[8] |hk_dat_i[8]
|
|
hk_dat_i[9] |hk_dat_i[9]
|
|
hk_stb_o |hk_stb_o
|
|
irq[3] |irq[3]
|
|
irq[4] |irq[4]
|
|
irq[5] |irq[5]
|
|
qspi_enabled |qspi_enabled
|
|
ser_rx |ser_rx
|
|
ser_tx |ser_tx
|
|
spi_csb |spi_csb
|
|
spi_enabled |spi_enabled
|
|
spi_sck |spi_sck
|
|
spi_sdi |spi_sdi
|
|
spi_sdo |spi_sdo
|
|
spi_sdoenb |spi_sdoenb
|
|
tck |tck
|
|
tdi |tdi
|
|
tdo |tdo
|
|
tms |tms
|
|
trap |trap
|
|
trst |trst
|
|
uart_enabled |uart_enabled
|
|
VGND |VGND
|
|
VPWR |VPWR
|
|
tdo_paden_o |(no matching pin)
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mgmt_core_wrapper and mgmt_core_wrapper are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6) |sky130_fd_pr__pfet_01v8_hvt (6)
|
|
sky130_fd_pr__nfet_01v8 (6) |sky130_fd_pr__nfet_01v8 (6)
|
|
Number of devices: 12 |Number of devices: 12
|
|
Number of nets: 11 |Number of nets: 11
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__dlymetal6s2s_1 |Circuit 2: sky130_fd_sc_hd__dlymetal6s2s_1
|
|
-------------------------------------------|-------------------------------------------
|
|
A |A
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
X |X
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__dlymetal6s2s_1 and sky130_fd_sc_hd__dlymetal6s2s_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__dfrtp_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__dfrtp_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (17->14) |sky130_fd_pr__nfet_01v8 (17->14)
|
|
sky130_fd_pr__pfet_01v8_hvt (17->14) |sky130_fd_pr__pfet_01v8_hvt (17->14)
|
|
Number of devices: 28 |Number of devices: 28
|
|
Number of nets: 21 |Number of nets: 21
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__dfrtp_4 |Circuit 2: sky130_fd_sc_hd__dfrtp_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
RESET_B |RESET_B
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VGND |VGND
|
|
D |D
|
|
Q |Q
|
|
CLK |CLK
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__dfrtp_4 and sky130_fd_sc_hd__dfrtp_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2b_4 (0): Merged 12 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2b_4 (1): Merged 12 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (9->3) |sky130_fd_pr__nfet_01v8 (9->3)
|
|
sky130_fd_pr__pfet_01v8_hvt (9->3) |sky130_fd_pr__pfet_01v8_hvt (9->3)
|
|
Number of devices: 6 |Number of devices: 6
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2b_4 |Circuit 2: sky130_fd_sc_hd__nand2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
Y |Y
|
|
VPB |VPB
|
|
VNB |VNB
|
|
B |B
|
|
VGND |VGND
|
|
A_N |A_N
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2b_4 and sky130_fd_sc_hd__nand2b_4 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__mux2_8 (0): Merged 22 parallel devices.
|
|
Class sky130_fd_sc_hd__mux2_8 (1): Merged 22 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (17->6) |sky130_fd_pr__nfet_01v8 (17->6)
|
|
sky130_fd_pr__pfet_01v8_hvt (17->6) |sky130_fd_pr__pfet_01v8_hvt (17->6)
|
|
Number of devices: 12 |Number of devices: 12
|
|
Number of nets: 14 |Number of nets: 14
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_8 |Circuit 2: sky130_fd_sc_hd__mux2_8
|
|
-------------------------------------------|-------------------------------------------
|
|
X |X
|
|
A0 |A0
|
|
A1 |A1
|
|
VNB |VNB
|
|
VPB |VPB
|
|
VGND |VGND
|
|
S |S
|
|
VPWR |VPWR
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__mux2_8 and sky130_fd_sc_hd__mux2_8 are equivalent.
|
|
|
|
Circuit 2 cell simple_por is a black box; will not flatten Circuit 1
|
|
Warning: Equate pins: cell simple_por is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: simple_por |Circuit 2: simple_por
|
|
-------------------------------------------|-------------------------------------------
|
|
vss1v8 |vss1v8
|
|
vdd3v3 |vdd3v3
|
|
vdd1v8 |vdd1v8
|
|
porb_h |porb_h
|
|
por_l |por_l
|
|
porb_l |porb_l
|
|
vss3v3 |vss3v3
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes simple_por and simple_por are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__dfbbn_1 |Circuit 2: sky130_fd_sc_hd__dfbbn_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (20) |sky130_fd_pr__nfet_01v8 (20)
|
|
sky130_fd_pr__pfet_01v8_hvt (20) |sky130_fd_pr__pfet_01v8_hvt (20)
|
|
Number of devices: 40 |Number of devices: 40
|
|
Number of nets: 29 |Number of nets: 29
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__dfbbn_1 |Circuit 2: sky130_fd_sc_hd__dfbbn_1
|
|
-------------------------------------------|-------------------------------------------
|
|
D |D
|
|
RESET_B |RESET_B
|
|
Q |Q
|
|
Q_N |Q_N
|
|
CLK_N |CLK_N
|
|
VPWR |VPWR
|
|
VNB |VNB
|
|
VPB |VPB
|
|
VGND |VGND
|
|
SET_B |SET_B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__dfbbn_1 and sky130_fd_sc_hd__dfbbn_1 are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__mux2_2 (0): Merged 2 parallel devices.
|
|
Class sky130_fd_sc_hd__mux2_2 (1): Merged 2 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (7->6) |sky130_fd_pr__pfet_01v8_hvt (7->6)
|
|
sky130_fd_pr__nfet_01v8 (7->6) |sky130_fd_pr__nfet_01v8 (7->6)
|
|
Number of devices: 12 |Number of devices: 12
|
|
Number of nets: 14 |Number of nets: 14
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__mux2_2 |Circuit 2: sky130_fd_sc_hd__mux2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VNB |VNB
|
|
VPB |VPB
|
|
A1 |A1
|
|
A0 |A0
|
|
X |X
|
|
VGND |VGND
|
|
VPWR |VPWR
|
|
S |S
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__mux2_2 and sky130_fd_sc_hd__mux2_2 are equivalent.
|
|
|
|
Circuit 2 cell caravel_clocking is a black box; will not flatten Circuit 1
|
|
Class caravel_clocking (0): Merged 505 parallel devices.
|
|
Warning: Equate pins: cell caravel_clocking is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: caravel_clocking |Circuit 2: caravel_clocking
|
|
-------------------------------------------|-------------------------------------------
|
|
core_clk |core_clk
|
|
ext_clk |ext_clk
|
|
pll_clk |pll_clk
|
|
pll_clk90 |pll_clk90
|
|
resetb |resetb
|
|
resetb_sync |resetb_sync
|
|
user_clk |user_clk
|
|
ext_clk_sel |ext_clk_sel
|
|
ext_reset |ext_reset
|
|
porb |porb
|
|
sel2[0] |sel2[0]
|
|
sel2[1] |sel2[1]
|
|
sel2[2] |sel2[2]
|
|
sel[0] |sel[0]
|
|
sel[1] |sel[1]
|
|
sel[2] |sel[2]
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes caravel_clocking and caravel_clocking are equivalent.
|
|
|
|
Circuit 2 cell spare_logic_block is a black box; will not flatten Circuit 1
|
|
Class spare_logic_block (0): Merged 88 parallel devices.
|
|
Warning: Equate pins: cell spare_logic_block is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: spare_logic_block |Circuit 2: spare_logic_block
|
|
-------------------------------------------|-------------------------------------------
|
|
spare_xfq[1] |spare_xfq[1]
|
|
spare_xfqn[0] |spare_xfqn[0]
|
|
spare_xi[0] |spare_xi[0]
|
|
spare_xi[3] |spare_xi[3]
|
|
spare_xmx[0] |spare_xmx[0]
|
|
spare_xmx[1] |spare_xmx[1]
|
|
spare_xno[0] |spare_xno[0]
|
|
spare_xz[10] |spare_xz[10]
|
|
spare_xz[11] |spare_xz[11]
|
|
spare_xz[14] |spare_xz[14]
|
|
spare_xz[15] |spare_xz[15]
|
|
spare_xz[18] |spare_xz[18]
|
|
spare_xz[1] |spare_xz[1]
|
|
spare_xz[20] |spare_xz[20]
|
|
spare_xz[22] |spare_xz[22]
|
|
spare_xz[23] |spare_xz[23]
|
|
spare_xz[24] |spare_xz[24]
|
|
spare_xz[26] |spare_xz[26]
|
|
spare_xz[3] |spare_xz[3]
|
|
spare_xz[4] |spare_xz[4]
|
|
spare_xz[5] |spare_xz[5]
|
|
spare_xz[6] |spare_xz[6]
|
|
spare_xfq[0] |spare_xfq[0]
|
|
spare_xfqn[1] |spare_xfqn[1]
|
|
spare_xi[1] |spare_xi[1]
|
|
spare_xi[2] |spare_xi[2]
|
|
spare_xib |spare_xib
|
|
spare_xna[0] |spare_xna[0]
|
|
spare_xna[1] |spare_xna[1]
|
|
spare_xno[1] |spare_xno[1]
|
|
spare_xz[0] |spare_xz[0]
|
|
spare_xz[12] |spare_xz[12]
|
|
spare_xz[13] |spare_xz[13]
|
|
spare_xz[16] |spare_xz[16]
|
|
spare_xz[17] |spare_xz[17]
|
|
spare_xz[19] |spare_xz[19]
|
|
spare_xz[21] |spare_xz[21]
|
|
spare_xz[25] |spare_xz[25]
|
|
spare_xz[2] |spare_xz[2]
|
|
spare_xz[7] |spare_xz[7]
|
|
spare_xz[8] |spare_xz[8]
|
|
spare_xz[9] |spare_xz[9]
|
|
vccd |vccd
|
|
vssd |vssd
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes spare_logic_block and spare_logic_block are equivalent.
|
|
|
|
Circuit 2 cell user_id_programming is a black box; will not flatten Circuit 1
|
|
Class user_id_programming (0): Merged 54 parallel devices.
|
|
Warning: Equate pins: cell user_id_programming is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: user_id_programming |Circuit 2: user_id_programming
|
|
-------------------------------------------|-------------------------------------------
|
|
mask_rev[0] |mask_rev[0]
|
|
mask_rev[10] |mask_rev[10]
|
|
mask_rev[11] |mask_rev[11]
|
|
mask_rev[12] |mask_rev[12]
|
|
mask_rev[13] |mask_rev[13]
|
|
mask_rev[14] |mask_rev[14]
|
|
mask_rev[16] |mask_rev[16]
|
|
mask_rev[17] |mask_rev[17]
|
|
mask_rev[19] |mask_rev[19]
|
|
mask_rev[23] |mask_rev[23]
|
|
mask_rev[24] |mask_rev[24]
|
|
mask_rev[26] |mask_rev[26]
|
|
mask_rev[27] |mask_rev[27]
|
|
mask_rev[28] |mask_rev[28]
|
|
mask_rev[29] |mask_rev[29]
|
|
mask_rev[31] |mask_rev[31]
|
|
mask_rev[3] |mask_rev[3]
|
|
mask_rev[7] |mask_rev[7]
|
|
mask_rev[8] |mask_rev[8]
|
|
mask_rev[9] |mask_rev[9]
|
|
mask_rev[15] |mask_rev[15]
|
|
mask_rev[18] |mask_rev[18]
|
|
mask_rev[1] |mask_rev[1]
|
|
mask_rev[20] |mask_rev[20]
|
|
mask_rev[21] |mask_rev[21]
|
|
mask_rev[22] |mask_rev[22]
|
|
mask_rev[25] |mask_rev[25]
|
|
mask_rev[2] |mask_rev[2]
|
|
mask_rev[30] |mask_rev[30]
|
|
mask_rev[4] |mask_rev[4]
|
|
mask_rev[5] |mask_rev[5]
|
|
mask_rev[6] |mask_rev[6]
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes user_id_programming and user_id_programming are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__nand2_2 (0): Merged 4 parallel devices.
|
|
Class sky130_fd_sc_hd__nand2_2 (1): Merged 4 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4->2) |sky130_fd_pr__pfet_01v8_hvt (4->2)
|
|
sky130_fd_pr__nfet_01v8 (4->2) |sky130_fd_pr__nfet_01v8 (4->2)
|
|
Number of devices: 4 |Number of devices: 4
|
|
Number of nets: 8 |Number of nets: 8
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__nand2_2 |Circuit 2: sky130_fd_sc_hd__nand2_2
|
|
-------------------------------------------|-------------------------------------------
|
|
VGND |VGND
|
|
Y |Y
|
|
A |A
|
|
VNB |VNB
|
|
B |B
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__nand2_2 and sky130_fd_sc_hd__nand2_2 are equivalent.
|
|
|
|
Circuit 2 cell mprj2_logic_high is a black box; will not flatten Circuit 1
|
|
Class mprj2_logic_high (0): Merged 44 parallel devices.
|
|
Warning: Equate pins: cell mprj2_logic_high is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mprj2_logic_high |Circuit 2: mprj2_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd2 |vccd2
|
|
HI |HI
|
|
vssd2 |vssd2
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mprj2_logic_high and mprj2_logic_high are equivalent.
|
|
|
|
Circuit 2 cell mprj_io_buffer is a black box; will not flatten Circuit 1
|
|
Class mprj_io_buffer (0): Merged 98 parallel devices.
|
|
Warning: Equate pins: cell mprj_io_buffer is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mprj_io_buffer |Circuit 2: mprj_io_buffer
|
|
-------------------------------------------|-------------------------------------------
|
|
mgmt_gpio_in[0] |mgmt_gpio_in[0]
|
|
mgmt_gpio_in[10] |mgmt_gpio_in[10]
|
|
mgmt_gpio_in[11] |mgmt_gpio_in[11]
|
|
mgmt_gpio_in[12] |mgmt_gpio_in[12]
|
|
mgmt_gpio_in[13] |mgmt_gpio_in[13]
|
|
mgmt_gpio_in[1] |mgmt_gpio_in[1]
|
|
mgmt_gpio_in[2] |mgmt_gpio_in[2]
|
|
mgmt_gpio_in[3] |mgmt_gpio_in[3]
|
|
mgmt_gpio_in[4] |mgmt_gpio_in[4]
|
|
mgmt_gpio_in[5] |mgmt_gpio_in[5]
|
|
mgmt_gpio_in[6] |mgmt_gpio_in[6]
|
|
mgmt_gpio_in[7] |mgmt_gpio_in[7]
|
|
mgmt_gpio_in[8] |mgmt_gpio_in[8]
|
|
mgmt_gpio_in[9] |mgmt_gpio_in[9]
|
|
mgmt_gpio_out[0] |mgmt_gpio_out[0]
|
|
mgmt_gpio_out[10] |mgmt_gpio_out[10]
|
|
mgmt_gpio_out[11] |mgmt_gpio_out[11]
|
|
mgmt_gpio_out[12] |mgmt_gpio_out[12]
|
|
mgmt_gpio_out[13] |mgmt_gpio_out[13]
|
|
mgmt_gpio_out[14] |mgmt_gpio_out[14]
|
|
mgmt_gpio_out[15] |mgmt_gpio_out[15]
|
|
mgmt_gpio_out[16] |mgmt_gpio_out[16]
|
|
mgmt_gpio_out[17] |mgmt_gpio_out[17]
|
|
mgmt_gpio_out[18] |mgmt_gpio_out[18]
|
|
mgmt_gpio_out[1] |mgmt_gpio_out[1]
|
|
mgmt_gpio_out[2] |mgmt_gpio_out[2]
|
|
mgmt_gpio_out[3] |mgmt_gpio_out[3]
|
|
mgmt_gpio_out[4] |mgmt_gpio_out[4]
|
|
mgmt_gpio_out[5] |mgmt_gpio_out[5]
|
|
mgmt_gpio_out[6] |mgmt_gpio_out[6]
|
|
mgmt_gpio_out[7] |mgmt_gpio_out[7]
|
|
mgmt_gpio_out[8] |mgmt_gpio_out[8]
|
|
mgmt_gpio_out[9] |mgmt_gpio_out[9]
|
|
mgmt_gpio_out_buf[0] |mgmt_gpio_out_buf[0]
|
|
mgmt_gpio_out_buf[10] |mgmt_gpio_out_buf[10]
|
|
mgmt_gpio_out_buf[11] |mgmt_gpio_out_buf[11]
|
|
mgmt_gpio_out_buf[12] |mgmt_gpio_out_buf[12]
|
|
mgmt_gpio_out_buf[13] |mgmt_gpio_out_buf[13]
|
|
mgmt_gpio_out_buf[1] |mgmt_gpio_out_buf[1]
|
|
mgmt_gpio_out_buf[2] |mgmt_gpio_out_buf[2]
|
|
mgmt_gpio_out_buf[3] |mgmt_gpio_out_buf[3]
|
|
mgmt_gpio_out_buf[4] |mgmt_gpio_out_buf[4]
|
|
mgmt_gpio_out_buf[5] |mgmt_gpio_out_buf[5]
|
|
mgmt_gpio_out_buf[6] |mgmt_gpio_out_buf[6]
|
|
mgmt_gpio_out_buf[7] |mgmt_gpio_out_buf[7]
|
|
mgmt_gpio_out_buf[8] |mgmt_gpio_out_buf[8]
|
|
mgmt_gpio_out_buf[9] |mgmt_gpio_out_buf[9]
|
|
mgmt_gpio_in[14] |mgmt_gpio_in[14]
|
|
mgmt_gpio_in[15] |mgmt_gpio_in[15]
|
|
mgmt_gpio_in[16] |mgmt_gpio_in[16]
|
|
mgmt_gpio_in[17] |mgmt_gpio_in[17]
|
|
mgmt_gpio_in[18] |mgmt_gpio_in[18]
|
|
mgmt_gpio_in_buf[0] |mgmt_gpio_in_buf[0]
|
|
mgmt_gpio_in_buf[10] |mgmt_gpio_in_buf[10]
|
|
mgmt_gpio_in_buf[11] |mgmt_gpio_in_buf[11]
|
|
mgmt_gpio_in_buf[12] |mgmt_gpio_in_buf[12]
|
|
mgmt_gpio_in_buf[13] |mgmt_gpio_in_buf[13]
|
|
mgmt_gpio_in_buf[14] |mgmt_gpio_in_buf[14]
|
|
mgmt_gpio_in_buf[15] |mgmt_gpio_in_buf[15]
|
|
mgmt_gpio_in_buf[16] |mgmt_gpio_in_buf[16]
|
|
mgmt_gpio_in_buf[17] |mgmt_gpio_in_buf[17]
|
|
mgmt_gpio_in_buf[18] |mgmt_gpio_in_buf[18]
|
|
mgmt_gpio_in_buf[1] |mgmt_gpio_in_buf[1]
|
|
mgmt_gpio_in_buf[2] |mgmt_gpio_in_buf[2]
|
|
mgmt_gpio_in_buf[3] |mgmt_gpio_in_buf[3]
|
|
mgmt_gpio_in_buf[4] |mgmt_gpio_in_buf[4]
|
|
mgmt_gpio_in_buf[5] |mgmt_gpio_in_buf[5]
|
|
mgmt_gpio_in_buf[6] |mgmt_gpio_in_buf[6]
|
|
mgmt_gpio_in_buf[7] |mgmt_gpio_in_buf[7]
|
|
mgmt_gpio_in_buf[8] |mgmt_gpio_in_buf[8]
|
|
mgmt_gpio_in_buf[9] |mgmt_gpio_in_buf[9]
|
|
mgmt_gpio_oeb[0] |mgmt_gpio_oeb[0]
|
|
mgmt_gpio_oeb[1] |mgmt_gpio_oeb[1]
|
|
mgmt_gpio_oeb[2] |mgmt_gpio_oeb[2]
|
|
mgmt_gpio_oeb_buf[0] |mgmt_gpio_oeb_buf[0]
|
|
mgmt_gpio_oeb_buf[1] |mgmt_gpio_oeb_buf[1]
|
|
mgmt_gpio_oeb_buf[2] |mgmt_gpio_oeb_buf[2]
|
|
mgmt_gpio_out_buf[14] |mgmt_gpio_out_buf[14]
|
|
mgmt_gpio_out_buf[15] |mgmt_gpio_out_buf[15]
|
|
mgmt_gpio_out_buf[16] |mgmt_gpio_out_buf[16]
|
|
mgmt_gpio_out_buf[17] |mgmt_gpio_out_buf[17]
|
|
mgmt_gpio_out_buf[18] |mgmt_gpio_out_buf[18]
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mprj_io_buffer and mprj_io_buffer are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__inv_6 (0): Merged 10 parallel devices.
|
|
Class sky130_fd_sc_hd__inv_6 (1): Merged 10 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (6->1) |sky130_fd_pr__pfet_01v8_hvt (6->1)
|
|
sky130_fd_pr__nfet_01v8 (6->1) |sky130_fd_pr__nfet_01v8 (6->1)
|
|
Number of devices: 2 |Number of devices: 2
|
|
Number of nets: 6 |Number of nets: 6
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__inv_6 |Circuit 2: sky130_fd_sc_hd__inv_6
|
|
-------------------------------------------|-------------------------------------------
|
|
A |A
|
|
Y |Y
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VGND |VGND
|
|
VNB |VNB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__inv_6 and sky130_fd_sc_hd__inv_6 are equivalent.
|
|
|
|
Circuit 2 cell xres_buf is a black box; will not flatten Circuit 1
|
|
Class xres_buf (0): Merged 5 parallel devices.
|
|
Warning: Equate pins: cell xres_buf is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: xres_buf |Circuit 2: xres_buf
|
|
-------------------------------------------|-------------------------------------------
|
|
LVPWR |LVPWR
|
|
LVGND |LVGND
|
|
A |A
|
|
X |X
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes xres_buf and xres_buf are equivalent.
|
|
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__pfet_01v8_hvt (4) |sky130_fd_pr__pfet_01v8_hvt (4)
|
|
sky130_fd_pr__nfet_01v8 (4) |sky130_fd_pr__nfet_01v8 (4)
|
|
Number of devices: 8 |Number of devices: 8
|
|
Number of nets: 9 |Number of nets: 9
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__dlygate4sd3_1 |Circuit 2: sky130_fd_sc_hd__dlygate4sd3_1
|
|
-------------------------------------------|-------------------------------------------
|
|
A |A
|
|
X |X
|
|
VGND |VGND
|
|
VNB |VNB
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__dlygate4sd3_1 and sky130_fd_sc_hd__dlygate4sd3_1 are equivalent.
|
|
|
|
Circuit 2 cell user_project_wrapper is a black box; will not flatten Circuit 1
|
|
Warning: Equate pins: cell user_project_wrapper is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd1 |vccd1
|
|
vccd2 |vccd2
|
|
vdda1 |vdda1
|
|
vdda2 |vdda2
|
|
vssa1 |vssa1
|
|
vssa2 |vssa2
|
|
vssd2 |vssd2
|
|
analog_io[10] |analog_io[10]
|
|
analog_io[11] |analog_io[11]
|
|
analog_io[12] |analog_io[12]
|
|
analog_io[8] |analog_io[8]
|
|
analog_io[9] |analog_io[9]
|
|
io_in[15] |io_in[15]
|
|
io_in[16] |io_in[16]
|
|
io_in[17] |io_in[17]
|
|
io_in[18] |io_in[18]
|
|
io_in[19] |io_in[19]
|
|
io_oeb[15] |io_oeb[15]
|
|
io_oeb[16] |io_oeb[16]
|
|
io_oeb[17] |io_oeb[17]
|
|
io_oeb[18] |io_oeb[18]
|
|
io_out[15] |io_out[15]
|
|
io_out[16] |io_out[16]
|
|
io_out[17] |io_out[17]
|
|
io_out[18] |io_out[18]
|
|
analog_io[16] |analog_io[16]
|
|
analog_io[13] |analog_io[13]
|
|
analog_io[14] |analog_io[14]
|
|
analog_io[15] |analog_io[15]
|
|
io_oeb[19] |io_oeb[19]
|
|
io_oeb[20] |io_oeb[20]
|
|
io_oeb[21] |io_oeb[21]
|
|
io_oeb[22] |io_oeb[22]
|
|
io_oeb[23] |io_oeb[23]
|
|
io_in[20] |io_in[20]
|
|
io_in[21] |io_in[21]
|
|
io_in[22] |io_in[22]
|
|
io_in[23] |io_in[23]
|
|
io_out[19] |io_out[19]
|
|
io_out[20] |io_out[20]
|
|
io_out[21] |io_out[21]
|
|
io_out[22] |io_out[22]
|
|
io_out[23] |io_out[23]
|
|
wb_clk_i |wb_clk_i
|
|
wb_rst_i |wb_rst_i
|
|
wbs_ack_o |wbs_ack_o
|
|
wbs_adr_i[0] |wbs_adr_i[0]
|
|
wbs_adr_i[10] |wbs_adr_i[10]
|
|
wbs_adr_i[11] |wbs_adr_i[11]
|
|
wbs_adr_i[12] |wbs_adr_i[12]
|
|
wbs_adr_i[13] |wbs_adr_i[13]
|
|
wbs_adr_i[14] |wbs_adr_i[14]
|
|
wbs_adr_i[15] |wbs_adr_i[15]
|
|
wbs_adr_i[16] |wbs_adr_i[16]
|
|
wbs_adr_i[17] |wbs_adr_i[17]
|
|
wbs_adr_i[1] |wbs_adr_i[1]
|
|
wbs_adr_i[2] |wbs_adr_i[2]
|
|
wbs_adr_i[3] |wbs_adr_i[3]
|
|
wbs_adr_i[4] |wbs_adr_i[4]
|
|
wbs_adr_i[5] |wbs_adr_i[5]
|
|
wbs_adr_i[6] |wbs_adr_i[6]
|
|
wbs_adr_i[7] |wbs_adr_i[7]
|
|
wbs_adr_i[8] |wbs_adr_i[8]
|
|
wbs_adr_i[9] |wbs_adr_i[9]
|
|
wbs_cyc_i |wbs_cyc_i
|
|
wbs_dat_i[0] |wbs_dat_i[0]
|
|
wbs_dat_i[10] |wbs_dat_i[10]
|
|
wbs_dat_i[11] |wbs_dat_i[11]
|
|
wbs_dat_i[12] |wbs_dat_i[12]
|
|
wbs_dat_i[13] |wbs_dat_i[13]
|
|
wbs_dat_i[14] |wbs_dat_i[14]
|
|
wbs_dat_i[15] |wbs_dat_i[15]
|
|
wbs_dat_i[16] |wbs_dat_i[16]
|
|
wbs_dat_i[1] |wbs_dat_i[1]
|
|
wbs_dat_i[2] |wbs_dat_i[2]
|
|
wbs_dat_i[3] |wbs_dat_i[3]
|
|
wbs_dat_i[4] |wbs_dat_i[4]
|
|
wbs_dat_i[5] |wbs_dat_i[5]
|
|
wbs_dat_i[6] |wbs_dat_i[6]
|
|
wbs_dat_i[7] |wbs_dat_i[7]
|
|
wbs_dat_i[8] |wbs_dat_i[8]
|
|
wbs_dat_i[9] |wbs_dat_i[9]
|
|
wbs_dat_o[0] |wbs_dat_o[0]
|
|
wbs_dat_o[10] |wbs_dat_o[10]
|
|
wbs_dat_o[11] |wbs_dat_o[11]
|
|
wbs_dat_o[12] |wbs_dat_o[12]
|
|
wbs_dat_o[13] |wbs_dat_o[13]
|
|
wbs_dat_o[14] |wbs_dat_o[14]
|
|
wbs_dat_o[15] |wbs_dat_o[15]
|
|
wbs_dat_o[16] |wbs_dat_o[16]
|
|
wbs_dat_o[1] |wbs_dat_o[1]
|
|
wbs_dat_o[2] |wbs_dat_o[2]
|
|
wbs_dat_o[3] |wbs_dat_o[3]
|
|
wbs_dat_o[4] |wbs_dat_o[4]
|
|
wbs_dat_o[5] |wbs_dat_o[5]
|
|
wbs_dat_o[6] |wbs_dat_o[6]
|
|
wbs_dat_o[7] |wbs_dat_o[7]
|
|
wbs_dat_o[8] |wbs_dat_o[8]
|
|
wbs_dat_o[9] |wbs_dat_o[9]
|
|
wbs_sel_i[0] |wbs_sel_i[0]
|
|
wbs_sel_i[1] |wbs_sel_i[1]
|
|
wbs_sel_i[2] |wbs_sel_i[2]
|
|
wbs_sel_i[3] |wbs_sel_i[3]
|
|
wbs_stb_i |wbs_stb_i
|
|
wbs_we_i |wbs_we_i
|
|
wbs_dat_i[17] |wbs_dat_i[17]
|
|
wbs_dat_i[18] |wbs_dat_i[18]
|
|
wbs_dat_i[19] |wbs_dat_i[19]
|
|
wbs_adr_i[18] |wbs_adr_i[18]
|
|
wbs_dat_i[20] |wbs_dat_i[20]
|
|
wbs_dat_i[21] |wbs_dat_i[21]
|
|
wbs_dat_i[22] |wbs_dat_i[22]
|
|
wbs_dat_i[23] |wbs_dat_i[23]
|
|
wbs_dat_i[24] |wbs_dat_i[24]
|
|
wbs_dat_i[25] |wbs_dat_i[25]
|
|
wbs_dat_i[26] |wbs_dat_i[26]
|
|
wbs_dat_i[27] |wbs_dat_i[27]
|
|
wbs_dat_i[28] |wbs_dat_i[28]
|
|
wbs_dat_i[29] |wbs_dat_i[29]
|
|
wbs_adr_i[19] |wbs_adr_i[19]
|
|
wbs_dat_i[30] |wbs_dat_i[30]
|
|
wbs_dat_i[31] |wbs_dat_i[31]
|
|
la_oenb[0] |la_oenb[0]
|
|
wbs_adr_i[20] |wbs_adr_i[20]
|
|
wbs_adr_i[21] |wbs_adr_i[21]
|
|
wbs_adr_i[22] |wbs_adr_i[22]
|
|
wbs_adr_i[23] |wbs_adr_i[23]
|
|
wbs_adr_i[24] |wbs_adr_i[24]
|
|
wbs_adr_i[25] |wbs_adr_i[25]
|
|
wbs_adr_i[26] |wbs_adr_i[26]
|
|
wbs_adr_i[27] |wbs_adr_i[27]
|
|
wbs_adr_i[28] |wbs_adr_i[28]
|
|
wbs_adr_i[29] |wbs_adr_i[29]
|
|
la_oenb[1] |la_oenb[1]
|
|
wbs_adr_i[30] |wbs_adr_i[30]
|
|
wbs_adr_i[31] |wbs_adr_i[31]
|
|
la_oenb[2] |la_oenb[2]
|
|
wbs_dat_o[17] |wbs_dat_o[17]
|
|
wbs_dat_o[18] |wbs_dat_o[18]
|
|
wbs_dat_o[19] |wbs_dat_o[19]
|
|
la_oenb[3] |la_oenb[3]
|
|
wbs_dat_o[20] |wbs_dat_o[20]
|
|
wbs_dat_o[21] |wbs_dat_o[21]
|
|
wbs_dat_o[22] |wbs_dat_o[22]
|
|
wbs_dat_o[23] |wbs_dat_o[23]
|
|
wbs_dat_o[24] |wbs_dat_o[24]
|
|
wbs_dat_o[25] |wbs_dat_o[25]
|
|
wbs_dat_o[26] |wbs_dat_o[26]
|
|
wbs_dat_o[27] |wbs_dat_o[27]
|
|
wbs_dat_o[28] |wbs_dat_o[28]
|
|
wbs_dat_o[29] |wbs_dat_o[29]
|
|
la_oenb[4] |la_oenb[4]
|
|
wbs_dat_o[30] |wbs_dat_o[30]
|
|
wbs_dat_o[31] |wbs_dat_o[31]
|
|
la_oenb[5] |la_oenb[5]
|
|
la_data_in[0] |la_data_in[0]
|
|
la_data_in[1] |la_data_in[1]
|
|
la_data_in[2] |la_data_in[2]
|
|
la_data_in[3] |la_data_in[3]
|
|
la_data_in[4] |la_data_in[4]
|
|
la_data_in[5] |la_data_in[5]
|
|
la_data_out[0] |la_data_out[0]
|
|
la_data_out[1] |la_data_out[1]
|
|
la_data_out[2] |la_data_out[2]
|
|
la_data_out[3] |la_data_out[3]
|
|
la_data_out[4] |la_data_out[4]
|
|
la_data_out[5] |la_data_out[5]
|
|
la_data_in[23] |la_data_in[23]
|
|
la_data_in[24] |la_data_in[24]
|
|
la_data_in[25] |la_data_in[25]
|
|
la_oenb[6] |la_oenb[6]
|
|
la_oenb[7] |la_oenb[7]
|
|
la_oenb[8] |la_oenb[8]
|
|
la_oenb[9] |la_oenb[9]
|
|
la_data_in[26] |la_data_in[26]
|
|
la_data_in[11] |la_data_in[11]
|
|
la_data_in[12] |la_data_in[12]
|
|
la_data_in[13] |la_data_in[13]
|
|
la_data_in[14] |la_data_in[14]
|
|
la_data_in[6] |la_data_in[6]
|
|
la_data_in[7] |la_data_in[7]
|
|
la_data_in[8] |la_data_in[8]
|
|
la_data_in[9] |la_data_in[9]
|
|
la_data_in[15] |la_data_in[15]
|
|
la_data_out[10] |la_data_out[10]
|
|
la_data_out[11] |la_data_out[11]
|
|
la_data_out[12] |la_data_out[12]
|
|
la_data_out[13] |la_data_out[13]
|
|
la_data_out[14] |la_data_out[14]
|
|
la_data_out[15] |la_data_out[15]
|
|
la_data_out[16] |la_data_out[16]
|
|
la_data_out[17] |la_data_out[17]
|
|
la_data_out[18] |la_data_out[18]
|
|
la_data_out[19] |la_data_out[19]
|
|
la_data_in[16] |la_data_in[16]
|
|
la_data_out[20] |la_data_out[20]
|
|
la_data_out[21] |la_data_out[21]
|
|
la_data_out[22] |la_data_out[22]
|
|
la_data_out[23] |la_data_out[23]
|
|
la_data_out[24] |la_data_out[24]
|
|
la_data_out[25] |la_data_out[25]
|
|
la_data_in[17] |la_data_in[17]
|
|
la_data_in[18] |la_data_in[18]
|
|
la_data_in[19] |la_data_in[19]
|
|
la_data_in[10] |la_data_in[10]
|
|
la_data_out[6] |la_data_out[6]
|
|
la_data_out[7] |la_data_out[7]
|
|
la_data_out[8] |la_data_out[8]
|
|
la_data_out[9] |la_data_out[9]
|
|
la_data_in[20] |la_data_in[20]
|
|
la_oenb[10] |la_oenb[10]
|
|
la_oenb[11] |la_oenb[11]
|
|
la_oenb[12] |la_oenb[12]
|
|
la_oenb[13] |la_oenb[13]
|
|
la_oenb[14] |la_oenb[14]
|
|
la_oenb[15] |la_oenb[15]
|
|
la_oenb[16] |la_oenb[16]
|
|
la_oenb[17] |la_oenb[17]
|
|
la_oenb[18] |la_oenb[18]
|
|
la_oenb[19] |la_oenb[19]
|
|
la_data_in[21] |la_data_in[21]
|
|
la_oenb[20] |la_oenb[20]
|
|
la_oenb[21] |la_oenb[21]
|
|
la_oenb[22] |la_oenb[22]
|
|
la_oenb[23] |la_oenb[23]
|
|
la_oenb[24] |la_oenb[24]
|
|
la_oenb[25] |la_oenb[25]
|
|
la_data_in[22] |la_data_in[22]
|
|
la_data_in[39] |la_data_in[39]
|
|
la_oenb[45] |la_oenb[45]
|
|
la_data_in[40] |la_data_in[40]
|
|
la_data_out[26] |la_data_out[26]
|
|
la_data_out[27] |la_data_out[27]
|
|
la_data_out[28] |la_data_out[28]
|
|
la_data_out[29] |la_data_out[29]
|
|
la_data_in[41] |la_data_in[41]
|
|
la_data_out[30] |la_data_out[30]
|
|
la_data_out[31] |la_data_out[31]
|
|
la_data_out[32] |la_data_out[32]
|
|
la_data_out[33] |la_data_out[33]
|
|
la_data_out[34] |la_data_out[34]
|
|
la_data_out[35] |la_data_out[35]
|
|
la_data_out[36] |la_data_out[36]
|
|
la_data_out[37] |la_data_out[37]
|
|
la_data_out[38] |la_data_out[38]
|
|
la_data_out[39] |la_data_out[39]
|
|
la_data_in[42] |la_data_in[42]
|
|
la_data_out[40] |la_data_out[40]
|
|
la_data_out[41] |la_data_out[41]
|
|
la_data_out[42] |la_data_out[42]
|
|
la_data_out[43] |la_data_out[43]
|
|
la_data_out[44] |la_data_out[44]
|
|
la_data_out[45] |la_data_out[45]
|
|
la_data_out[46] |la_data_out[46]
|
|
la_data_in[43] |la_data_in[43]
|
|
la_data_in[44] |la_data_in[44]
|
|
la_data_in[45] |la_data_in[45]
|
|
la_data_in[46] |la_data_in[46]
|
|
la_oenb[46] |la_oenb[46]
|
|
la_oenb[38] |la_oenb[38]
|
|
la_oenb[39] |la_oenb[39]
|
|
la_oenb[37] |la_oenb[37]
|
|
la_oenb[40] |la_oenb[40]
|
|
la_oenb[41] |la_oenb[41]
|
|
la_oenb[42] |la_oenb[42]
|
|
la_oenb[43] |la_oenb[43]
|
|
la_data_in[27] |la_data_in[27]
|
|
la_data_in[28] |la_data_in[28]
|
|
la_data_in[29] |la_data_in[29]
|
|
la_oenb[44] |la_oenb[44]
|
|
la_data_in[30] |la_data_in[30]
|
|
la_data_in[31] |la_data_in[31]
|
|
la_data_in[32] |la_data_in[32]
|
|
la_data_in[33] |la_data_in[33]
|
|
la_data_in[34] |la_data_in[34]
|
|
la_data_in[35] |la_data_in[35]
|
|
la_data_in[36] |la_data_in[36]
|
|
la_data_in[37] |la_data_in[37]
|
|
la_oenb[26] |la_oenb[26]
|
|
la_oenb[27] |la_oenb[27]
|
|
la_oenb[28] |la_oenb[28]
|
|
la_oenb[29] |la_oenb[29]
|
|
la_data_in[38] |la_data_in[38]
|
|
la_oenb[30] |la_oenb[30]
|
|
la_oenb[31] |la_oenb[31]
|
|
la_oenb[32] |la_oenb[32]
|
|
la_oenb[33] |la_oenb[33]
|
|
la_oenb[34] |la_oenb[34]
|
|
la_oenb[35] |la_oenb[35]
|
|
la_oenb[36] |la_oenb[36]
|
|
la_oenb[47] |la_oenb[47]
|
|
la_oenb[48] |la_oenb[48]
|
|
la_oenb[49] |la_oenb[49]
|
|
la_oenb[50] |la_oenb[50]
|
|
la_oenb[51] |la_oenb[51]
|
|
la_oenb[52] |la_oenb[52]
|
|
la_oenb[53] |la_oenb[53]
|
|
la_oenb[54] |la_oenb[54]
|
|
la_oenb[55] |la_oenb[55]
|
|
la_oenb[56] |la_oenb[56]
|
|
la_oenb[57] |la_oenb[57]
|
|
la_oenb[58] |la_oenb[58]
|
|
la_oenb[59] |la_oenb[59]
|
|
la_oenb[60] |la_oenb[60]
|
|
la_oenb[61] |la_oenb[61]
|
|
la_oenb[62] |la_oenb[62]
|
|
la_oenb[63] |la_oenb[63]
|
|
la_oenb[64] |la_oenb[64]
|
|
la_oenb[65] |la_oenb[65]
|
|
la_oenb[66] |la_oenb[66]
|
|
la_data_in[47] |la_data_in[47]
|
|
la_data_in[48] |la_data_in[48]
|
|
la_data_in[49] |la_data_in[49]
|
|
la_data_in[50] |la_data_in[50]
|
|
la_data_in[51] |la_data_in[51]
|
|
la_data_in[52] |la_data_in[52]
|
|
la_data_in[53] |la_data_in[53]
|
|
la_data_in[54] |la_data_in[54]
|
|
la_data_in[55] |la_data_in[55]
|
|
la_data_in[56] |la_data_in[56]
|
|
la_data_in[57] |la_data_in[57]
|
|
la_data_in[58] |la_data_in[58]
|
|
la_data_in[59] |la_data_in[59]
|
|
la_data_in[60] |la_data_in[60]
|
|
la_data_in[61] |la_data_in[61]
|
|
la_data_in[62] |la_data_in[62]
|
|
la_data_in[63] |la_data_in[63]
|
|
la_data_out[47] |la_data_out[47]
|
|
la_data_out[48] |la_data_out[48]
|
|
la_data_out[49] |la_data_out[49]
|
|
la_data_in[64] |la_data_in[64]
|
|
la_data_out[50] |la_data_out[50]
|
|
la_data_out[51] |la_data_out[51]
|
|
la_data_out[52] |la_data_out[52]
|
|
la_data_out[53] |la_data_out[53]
|
|
la_data_out[54] |la_data_out[54]
|
|
la_data_out[55] |la_data_out[55]
|
|
la_data_out[56] |la_data_out[56]
|
|
la_data_out[57] |la_data_out[57]
|
|
la_data_out[58] |la_data_out[58]
|
|
la_data_out[59] |la_data_out[59]
|
|
la_data_in[65] |la_data_in[65]
|
|
la_data_out[60] |la_data_out[60]
|
|
la_data_out[61] |la_data_out[61]
|
|
la_data_out[62] |la_data_out[62]
|
|
la_data_out[63] |la_data_out[63]
|
|
la_data_out[64] |la_data_out[64]
|
|
la_data_out[65] |la_data_out[65]
|
|
la_data_out[66] |la_data_out[66]
|
|
la_data_out[67] |la_data_out[67]
|
|
la_data_in[66] |la_data_in[66]
|
|
la_data_in[67] |la_data_in[67]
|
|
la_data_in[72] |la_data_in[72]
|
|
la_data_in[73] |la_data_in[73]
|
|
la_data_in[74] |la_data_in[74]
|
|
la_data_in[75] |la_data_in[75]
|
|
la_data_in[76] |la_data_in[76]
|
|
la_data_in[77] |la_data_in[77]
|
|
la_data_in[78] |la_data_in[78]
|
|
la_data_in[79] |la_data_in[79]
|
|
la_data_in[80] |la_data_in[80]
|
|
la_data_in[81] |la_data_in[81]
|
|
la_data_in[82] |la_data_in[82]
|
|
la_data_in[83] |la_data_in[83]
|
|
la_data_in[84] |la_data_in[84]
|
|
la_data_in[85] |la_data_in[85]
|
|
la_data_in[86] |la_data_in[86]
|
|
la_data_in[87] |la_data_in[87]
|
|
la_data_in[69] |la_data_in[69]
|
|
la_oenb[67] |la_oenb[67]
|
|
la_oenb[68] |la_oenb[68]
|
|
la_oenb[69] |la_oenb[69]
|
|
la_oenb[70] |la_oenb[70]
|
|
la_oenb[71] |la_oenb[71]
|
|
la_oenb[72] |la_oenb[72]
|
|
la_oenb[73] |la_oenb[73]
|
|
la_oenb[74] |la_oenb[74]
|
|
la_oenb[75] |la_oenb[75]
|
|
la_oenb[76] |la_oenb[76]
|
|
la_oenb[77] |la_oenb[77]
|
|
la_oenb[78] |la_oenb[78]
|
|
la_oenb[79] |la_oenb[79]
|
|
la_oenb[80] |la_oenb[80]
|
|
la_oenb[81] |la_oenb[81]
|
|
la_oenb[82] |la_oenb[82]
|
|
la_oenb[83] |la_oenb[83]
|
|
la_oenb[84] |la_oenb[84]
|
|
la_oenb[85] |la_oenb[85]
|
|
la_oenb[86] |la_oenb[86]
|
|
la_oenb[87] |la_oenb[87]
|
|
la_data_out[68] |la_data_out[68]
|
|
la_data_out[69] |la_data_out[69]
|
|
la_data_in[70] |la_data_in[70]
|
|
la_data_out[70] |la_data_out[70]
|
|
la_data_out[71] |la_data_out[71]
|
|
la_data_out[72] |la_data_out[72]
|
|
la_data_out[73] |la_data_out[73]
|
|
la_data_out[74] |la_data_out[74]
|
|
la_data_out[75] |la_data_out[75]
|
|
la_data_out[76] |la_data_out[76]
|
|
la_data_out[77] |la_data_out[77]
|
|
la_data_out[78] |la_data_out[78]
|
|
la_data_out[79] |la_data_out[79]
|
|
la_data_in[71] |la_data_in[71]
|
|
la_data_out[80] |la_data_out[80]
|
|
la_data_out[81] |la_data_out[81]
|
|
la_data_out[82] |la_data_out[82]
|
|
la_data_out[83] |la_data_out[83]
|
|
la_data_out[84] |la_data_out[84]
|
|
la_data_out[85] |la_data_out[85]
|
|
la_data_out[86] |la_data_out[86]
|
|
la_data_out[87] |la_data_out[87]
|
|
la_data_in[68] |la_data_in[68]
|
|
la_oenb[88] |la_oenb[88]
|
|
la_oenb[89] |la_oenb[89]
|
|
la_oenb[90] |la_oenb[90]
|
|
la_oenb[91] |la_oenb[91]
|
|
la_oenb[92] |la_oenb[92]
|
|
la_oenb[93] |la_oenb[93]
|
|
la_oenb[94] |la_oenb[94]
|
|
la_oenb[95] |la_oenb[95]
|
|
la_oenb[96] |la_oenb[96]
|
|
la_oenb[97] |la_oenb[97]
|
|
la_oenb[98] |la_oenb[98]
|
|
la_oenb[99] |la_oenb[99]
|
|
la_data_in[101] |la_data_in[101]
|
|
la_data_in[102] |la_data_in[102]
|
|
la_data_in[103] |la_data_in[103]
|
|
la_data_in[104] |la_data_in[104]
|
|
la_data_in[105] |la_data_in[105]
|
|
la_data_in[106] |la_data_in[106]
|
|
la_data_in[107] |la_data_in[107]
|
|
la_data_in[108] |la_data_in[108]
|
|
la_data_in[100] |la_data_in[100]
|
|
la_data_in[90] |la_data_in[90]
|
|
la_data_in[91] |la_data_in[91]
|
|
la_data_in[92] |la_data_in[92]
|
|
la_data_in[93] |la_data_in[93]
|
|
la_data_in[94] |la_data_in[94]
|
|
la_data_in[95] |la_data_in[95]
|
|
la_data_in[96] |la_data_in[96]
|
|
la_data_in[97] |la_data_in[97]
|
|
la_data_in[98] |la_data_in[98]
|
|
la_data_in[99] |la_data_in[99]
|
|
la_data_out[100] |la_data_out[100]
|
|
la_data_out[101] |la_data_out[101]
|
|
la_data_out[102] |la_data_out[102]
|
|
la_data_out[103] |la_data_out[103]
|
|
la_data_out[104] |la_data_out[104]
|
|
la_data_out[105] |la_data_out[105]
|
|
la_data_out[93] |la_data_out[93]
|
|
la_data_out[106] |la_data_out[106]
|
|
la_data_out[94] |la_data_out[94]
|
|
la_data_out[107] |la_data_out[107]
|
|
la_data_out[95] |la_data_out[95]
|
|
la_data_out[96] |la_data_out[96]
|
|
la_data_out[108] |la_data_out[108]
|
|
la_data_out[97] |la_data_out[97]
|
|
la_data_out[98] |la_data_out[98]
|
|
la_data_out[99] |la_data_out[99]
|
|
la_data_out[92] |la_data_out[92]
|
|
la_oenb[100] |la_oenb[100]
|
|
la_oenb[101] |la_oenb[101]
|
|
la_oenb[102] |la_oenb[102]
|
|
la_oenb[103] |la_oenb[103]
|
|
la_oenb[104] |la_oenb[104]
|
|
la_oenb[105] |la_oenb[105]
|
|
la_oenb[106] |la_oenb[106]
|
|
la_oenb[107] |la_oenb[107]
|
|
la_data_in[88] |la_data_in[88]
|
|
la_data_in[89] |la_data_in[89]
|
|
la_data_out[88] |la_data_out[88]
|
|
la_data_out[89] |la_data_out[89]
|
|
la_data_out[90] |la_data_out[90]
|
|
la_data_out[91] |la_data_out[91]
|
|
la_data_in[119] |la_data_in[119]
|
|
la_data_out[120] |la_data_out[120]
|
|
la_data_out[121] |la_data_out[121]
|
|
la_data_out[122] |la_data_out[122]
|
|
la_data_in[116] |la_data_in[116]
|
|
la_data_in[117] |la_data_in[117]
|
|
la_data_out[123] |la_data_out[123]
|
|
la_data_in[112] |la_data_in[112]
|
|
la_data_out[124] |la_data_out[124]
|
|
la_data_out[125] |la_data_out[125]
|
|
la_data_out[126] |la_data_out[126]
|
|
la_data_out[127] |la_data_out[127]
|
|
la_data_in[118] |la_data_in[118]
|
|
la_oenb[109] |la_oenb[109]
|
|
la_data_in[120] |la_data_in[120]
|
|
la_oenb[110] |la_oenb[110]
|
|
la_data_in[121] |la_data_in[121]
|
|
la_oenb[111] |la_oenb[111]
|
|
la_oenb[112] |la_oenb[112]
|
|
la_oenb[113] |la_oenb[113]
|
|
la_oenb[114] |la_oenb[114]
|
|
la_oenb[115] |la_oenb[115]
|
|
la_oenb[116] |la_oenb[116]
|
|
la_oenb[117] |la_oenb[117]
|
|
la_oenb[118] |la_oenb[118]
|
|
la_oenb[119] |la_oenb[119]
|
|
la_data_in[122] |la_data_in[122]
|
|
la_data_in[123] |la_data_in[123]
|
|
la_oenb[120] |la_oenb[120]
|
|
la_oenb[121] |la_oenb[121]
|
|
la_oenb[122] |la_oenb[122]
|
|
la_oenb[123] |la_oenb[123]
|
|
la_oenb[124] |la_oenb[124]
|
|
la_oenb[125] |la_oenb[125]
|
|
la_oenb[126] |la_oenb[126]
|
|
la_oenb[127] |la_oenb[127]
|
|
la_data_in[124] |la_data_in[124]
|
|
la_data_in[125] |la_data_in[125]
|
|
la_data_in[126] |la_data_in[126]
|
|
la_data_in[127] |la_data_in[127]
|
|
la_data_out[110] |la_data_out[110]
|
|
user_clock2 |user_clock2
|
|
user_irq[0] |user_irq[0]
|
|
la_data_in[113] |la_data_in[113]
|
|
user_irq[1] |user_irq[1]
|
|
la_data_in[114] |la_data_in[114]
|
|
user_irq[2] |user_irq[2]
|
|
la_data_out[111] |la_data_out[111]
|
|
la_data_out[112] |la_data_out[112]
|
|
la_data_out[109] |la_data_out[109]
|
|
la_data_in[109] |la_data_in[109]
|
|
la_data_out[113] |la_data_out[113]
|
|
la_data_in[110] |la_data_in[110]
|
|
la_data_out[114] |la_data_out[114]
|
|
la_oenb[108] |la_oenb[108]
|
|
la_data_out[115] |la_data_out[115]
|
|
la_data_out[116] |la_data_out[116]
|
|
la_data_in[111] |la_data_in[111]
|
|
la_data_out[117] |la_data_out[117]
|
|
la_data_in[115] |la_data_in[115]
|
|
la_data_out[118] |la_data_out[118]
|
|
la_data_out[119] |la_data_out[119]
|
|
io_in[8] |io_in[8]
|
|
analog_io[3] |analog_io[3]
|
|
analog_io[4] |analog_io[4]
|
|
analog_io[5] |analog_io[5]
|
|
analog_io[6] |analog_io[6]
|
|
analog_io[7] |analog_io[7]
|
|
io_in[10] |io_in[10]
|
|
io_in[11] |io_in[11]
|
|
io_in[12] |io_in[12]
|
|
io_in[13] |io_in[13]
|
|
io_in[14] |io_in[14]
|
|
analog_io[2] |analog_io[2]
|
|
io_in[9] |io_in[9]
|
|
io_oeb[10] |io_oeb[10]
|
|
io_oeb[11] |io_oeb[11]
|
|
io_oeb[12] |io_oeb[12]
|
|
io_oeb[13] |io_oeb[13]
|
|
io_oeb[14] |io_oeb[14]
|
|
io_oeb[8] |io_oeb[8]
|
|
io_oeb[9] |io_oeb[9]
|
|
io_out[10] |io_out[10]
|
|
io_out[11] |io_out[11]
|
|
io_out[12] |io_out[12]
|
|
io_out[13] |io_out[13]
|
|
io_out[14] |io_out[14]
|
|
io_out[8] |io_out[8]
|
|
io_out[9] |io_out[9]
|
|
analog_io[23] |analog_io[23]
|
|
analog_io[17] |analog_io[17]
|
|
analog_io[18] |analog_io[18]
|
|
analog_io[19] |analog_io[19]
|
|
analog_io[20] |analog_io[20]
|
|
io_oeb[24] |io_oeb[24]
|
|
io_oeb[25] |io_oeb[25]
|
|
io_oeb[26] |io_oeb[26]
|
|
io_oeb[27] |io_oeb[27]
|
|
io_oeb[28] |io_oeb[28]
|
|
io_oeb[29] |io_oeb[29]
|
|
io_in[24] |io_in[24]
|
|
io_in[25] |io_in[25]
|
|
io_in[26] |io_in[26]
|
|
io_in[27] |io_in[27]
|
|
io_in[28] |io_in[28]
|
|
io_in[29] |io_in[29]
|
|
io_in[30] |io_in[30]
|
|
io_out[24] |io_out[24]
|
|
io_out[25] |io_out[25]
|
|
io_out[26] |io_out[26]
|
|
io_out[27] |io_out[27]
|
|
io_out[28] |io_out[28]
|
|
io_out[29] |io_out[29]
|
|
io_out[30] |io_out[30]
|
|
analog_io[21] |analog_io[21]
|
|
analog_io[22] |analog_io[22]
|
|
io_oeb[34] |io_oeb[34]
|
|
io_oeb[35] |io_oeb[35]
|
|
io_oeb[36] |io_oeb[36]
|
|
io_oeb[37] |io_oeb[37]
|
|
analog_io[28] |analog_io[28]
|
|
analog_io[24] |analog_io[24]
|
|
analog_io[25] |analog_io[25]
|
|
analog_io[26] |analog_io[26]
|
|
io_in[31] |io_in[31]
|
|
io_in[32] |io_in[32]
|
|
io_in[33] |io_in[33]
|
|
io_in[34] |io_in[34]
|
|
io_in[35] |io_in[35]
|
|
io_in[36] |io_in[36]
|
|
io_in[37] |io_in[37]
|
|
analog_io[27] |analog_io[27]
|
|
io_oeb[30] |io_oeb[30]
|
|
io_oeb[31] |io_oeb[31]
|
|
io_out[31] |io_out[31]
|
|
io_out[32] |io_out[32]
|
|
io_out[33] |io_out[33]
|
|
io_out[34] |io_out[34]
|
|
io_out[35] |io_out[35]
|
|
io_out[36] |io_out[36]
|
|
io_out[37] |io_out[37]
|
|
io_oeb[32] |io_oeb[32]
|
|
io_oeb[33] |io_oeb[33]
|
|
io_oeb[2] |io_oeb[2]
|
|
analog_io[0] |analog_io[0]
|
|
io_in[1] |io_in[1]
|
|
io_out[1] |io_out[1]
|
|
io_in[0] |io_in[0]
|
|
io_in[3] |io_in[3]
|
|
io_in[4] |io_in[4]
|
|
io_oeb[1] |io_oeb[1]
|
|
io_in[5] |io_in[5]
|
|
io_in[6] |io_in[6]
|
|
io_out[2] |io_out[2]
|
|
io_oeb[3] |io_oeb[3]
|
|
io_oeb[4] |io_oeb[4]
|
|
io_oeb[5] |io_oeb[5]
|
|
io_oeb[6] |io_oeb[6]
|
|
io_oeb[7] |io_oeb[7]
|
|
io_in[7] |io_in[7]
|
|
analog_io[1] |analog_io[1]
|
|
io_out[0] |io_out[0]
|
|
io_out[3] |io_out[3]
|
|
io_out[4] |io_out[4]
|
|
io_out[5] |io_out[5]
|
|
io_out[6] |io_out[6]
|
|
io_out[7] |io_out[7]
|
|
io_in[2] |io_in[2]
|
|
io_oeb[0] |io_oeb[0]
|
|
vssd1 |vssd1
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes user_project_wrapper and user_project_wrapper are equivalent.
|
|
|
|
Circuit 2 cell housekeeping_alt is a black box; will not flatten Circuit 1
|
|
Class housekeeping_alt (0): Merged 12349 parallel devices.
|
|
Warning: Equate pins: cell housekeeping_alt is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: housekeeping_alt |Circuit 2: housekeeping_alt
|
|
-------------------------------------------|-------------------------------------------
|
|
pll_trim[18] |pll_trim[18]
|
|
mgmt_gpio_in[21] |mgmt_gpio_in[21]
|
|
mgmt_gpio_in[22] |mgmt_gpio_in[22]
|
|
mgmt_gpio_in[23] |mgmt_gpio_in[23]
|
|
mgmt_gpio_in[24] |mgmt_gpio_in[24]
|
|
mgmt_gpio_in[25] |mgmt_gpio_in[25]
|
|
mgmt_gpio_in[26] |mgmt_gpio_in[26]
|
|
mgmt_gpio_in[27] |mgmt_gpio_in[27]
|
|
mgmt_gpio_in[28] |mgmt_gpio_in[28]
|
|
mgmt_gpio_in[29] |mgmt_gpio_in[29]
|
|
mgmt_gpio_in[30] |mgmt_gpio_in[30]
|
|
mgmt_gpio_in[31] |mgmt_gpio_in[31]
|
|
mgmt_gpio_in[32] |mgmt_gpio_in[32]
|
|
mgmt_gpio_in[33] |mgmt_gpio_in[33]
|
|
mgmt_gpio_in[34] |mgmt_gpio_in[34]
|
|
mgmt_gpio_in[35] |mgmt_gpio_in[35]
|
|
mgmt_gpio_in[36] |mgmt_gpio_in[36]
|
|
mgmt_gpio_in[37] |mgmt_gpio_in[37]
|
|
mgmt_gpio_oeb[20] |mgmt_gpio_oeb[20]
|
|
mgmt_gpio_oeb[21] |mgmt_gpio_oeb[21]
|
|
mgmt_gpio_oeb[22] |mgmt_gpio_oeb[22]
|
|
mgmt_gpio_oeb[23] |mgmt_gpio_oeb[23]
|
|
mgmt_gpio_oeb[24] |mgmt_gpio_oeb[24]
|
|
mgmt_gpio_oeb[25] |mgmt_gpio_oeb[25]
|
|
mgmt_gpio_oeb[26] |mgmt_gpio_oeb[26]
|
|
mgmt_gpio_oeb[27] |mgmt_gpio_oeb[27]
|
|
mgmt_gpio_oeb[28] |mgmt_gpio_oeb[28]
|
|
mgmt_gpio_oeb[29] |mgmt_gpio_oeb[29]
|
|
mgmt_gpio_oeb[30] |mgmt_gpio_oeb[30]
|
|
mgmt_gpio_oeb[31] |mgmt_gpio_oeb[31]
|
|
mgmt_gpio_oeb[32] |mgmt_gpio_oeb[32]
|
|
mgmt_gpio_oeb[33] |mgmt_gpio_oeb[33]
|
|
mgmt_gpio_oeb[34] |mgmt_gpio_oeb[34]
|
|
mgmt_gpio_oeb[35] |mgmt_gpio_oeb[35]
|
|
mgmt_gpio_oeb[36] |mgmt_gpio_oeb[36]
|
|
mgmt_gpio_oeb[37] |mgmt_gpio_oeb[37]
|
|
mgmt_gpio_out[20] |mgmt_gpio_out[20]
|
|
mgmt_gpio_out[21] |mgmt_gpio_out[21]
|
|
mgmt_gpio_out[22] |mgmt_gpio_out[22]
|
|
mgmt_gpio_out[23] |mgmt_gpio_out[23]
|
|
mgmt_gpio_out[24] |mgmt_gpio_out[24]
|
|
mgmt_gpio_out[25] |mgmt_gpio_out[25]
|
|
mgmt_gpio_out[26] |mgmt_gpio_out[26]
|
|
mgmt_gpio_out[27] |mgmt_gpio_out[27]
|
|
mgmt_gpio_out[28] |mgmt_gpio_out[28]
|
|
mgmt_gpio_out[29] |mgmt_gpio_out[29]
|
|
mgmt_gpio_out[30] |mgmt_gpio_out[30]
|
|
mgmt_gpio_out[31] |mgmt_gpio_out[31]
|
|
mgmt_gpio_out[32] |mgmt_gpio_out[32]
|
|
mgmt_gpio_out[33] |mgmt_gpio_out[33]
|
|
mgmt_gpio_out[34] |mgmt_gpio_out[34]
|
|
mgmt_gpio_out[35] |mgmt_gpio_out[35]
|
|
mgmt_gpio_out[36] |mgmt_gpio_out[36]
|
|
mgmt_gpio_out[37] |mgmt_gpio_out[37]
|
|
mgmt_gpio_in[20] |mgmt_gpio_in[20]
|
|
usr1_vcc_pwrgood |usr1_vcc_pwrgood
|
|
usr1_vdd_pwrgood |usr1_vdd_pwrgood
|
|
usr2_vcc_pwrgood |usr2_vcc_pwrgood
|
|
usr2_vdd_pwrgood |usr2_vdd_pwrgood
|
|
wb_cyc_i |wb_cyc_i
|
|
wb_sel_i[0] |wb_sel_i[0]
|
|
wb_sel_i[1] |wb_sel_i[1]
|
|
wb_sel_i[2] |wb_sel_i[2]
|
|
wb_sel_i[3] |wb_sel_i[3]
|
|
wb_we_i |wb_we_i
|
|
wb_adr_i[15] |wb_adr_i[15]
|
|
wb_adr_i[16] |wb_adr_i[16]
|
|
wb_adr_i[17] |wb_adr_i[17]
|
|
wb_adr_i[18] |wb_adr_i[18]
|
|
wb_adr_i[19] |wb_adr_i[19]
|
|
wb_adr_i[1] |wb_adr_i[1]
|
|
wb_adr_i[20] |wb_adr_i[20]
|
|
wb_adr_i[21] |wb_adr_i[21]
|
|
wb_adr_i[22] |wb_adr_i[22]
|
|
wb_adr_i[23] |wb_adr_i[23]
|
|
wb_adr_i[24] |wb_adr_i[24]
|
|
wb_adr_i[25] |wb_adr_i[25]
|
|
wb_adr_i[26] |wb_adr_i[26]
|
|
wb_adr_i[27] |wb_adr_i[27]
|
|
wb_adr_i[28] |wb_adr_i[28]
|
|
wb_adr_i[29] |wb_adr_i[29]
|
|
wb_adr_i[2] |wb_adr_i[2]
|
|
wb_adr_i[30] |wb_adr_i[30]
|
|
wb_adr_i[31] |wb_adr_i[31]
|
|
wb_adr_i[3] |wb_adr_i[3]
|
|
wb_adr_i[4] |wb_adr_i[4]
|
|
wb_adr_i[5] |wb_adr_i[5]
|
|
wb_adr_i[6] |wb_adr_i[6]
|
|
wb_adr_i[7] |wb_adr_i[7]
|
|
wb_adr_i[8] |wb_adr_i[8]
|
|
wb_adr_i[9] |wb_adr_i[9]
|
|
wb_adr_i[0] |wb_adr_i[0]
|
|
wb_dat_i[0] |wb_dat_i[0]
|
|
wb_dat_i[10] |wb_dat_i[10]
|
|
wb_dat_i[11] |wb_dat_i[11]
|
|
wb_dat_i[12] |wb_dat_i[12]
|
|
wb_dat_i[13] |wb_dat_i[13]
|
|
wb_dat_i[14] |wb_dat_i[14]
|
|
wb_dat_i[15] |wb_dat_i[15]
|
|
wb_dat_i[16] |wb_dat_i[16]
|
|
wb_dat_i[17] |wb_dat_i[17]
|
|
wb_dat_i[18] |wb_dat_i[18]
|
|
wb_dat_i[19] |wb_dat_i[19]
|
|
wb_dat_i[1] |wb_dat_i[1]
|
|
wb_dat_i[20] |wb_dat_i[20]
|
|
wb_dat_i[21] |wb_dat_i[21]
|
|
wb_dat_i[22] |wb_dat_i[22]
|
|
wb_dat_i[23] |wb_dat_i[23]
|
|
wb_dat_i[24] |wb_dat_i[24]
|
|
wb_dat_i[25] |wb_dat_i[25]
|
|
wb_dat_i[26] |wb_dat_i[26]
|
|
wb_dat_i[27] |wb_dat_i[27]
|
|
wb_dat_i[28] |wb_dat_i[28]
|
|
wb_dat_i[29] |wb_dat_i[29]
|
|
wb_dat_i[2] |wb_dat_i[2]
|
|
wb_dat_i[30] |wb_dat_i[30]
|
|
wb_dat_i[31] |wb_dat_i[31]
|
|
wb_dat_i[3] |wb_dat_i[3]
|
|
wb_dat_i[4] |wb_dat_i[4]
|
|
wb_dat_i[5] |wb_dat_i[5]
|
|
wb_dat_i[6] |wb_dat_i[6]
|
|
wb_dat_i[7] |wb_dat_i[7]
|
|
wb_dat_i[8] |wb_dat_i[8]
|
|
wb_dat_i[9] |wb_dat_i[9]
|
|
wb_adr_i[10] |wb_adr_i[10]
|
|
wb_adr_i[11] |wb_adr_i[11]
|
|
wb_adr_i[12] |wb_adr_i[12]
|
|
wb_adr_i[13] |wb_adr_i[13]
|
|
wb_adr_i[14] |wb_adr_i[14]
|
|
pll_trim[13] |pll_trim[13]
|
|
pll_trim[14] |pll_trim[14]
|
|
pll_trim[15] |pll_trim[15]
|
|
pll_trim[16] |pll_trim[16]
|
|
pll_trim[17] |pll_trim[17]
|
|
pad_flash_clk |pad_flash_clk
|
|
pll_trim[1] |pll_trim[1]
|
|
pll_trim[2] |pll_trim[2]
|
|
pll_trim[3] |pll_trim[3]
|
|
pll_trim[4] |pll_trim[4]
|
|
pll_trim[5] |pll_trim[5]
|
|
pll_trim[6] |pll_trim[6]
|
|
pll_trim[7] |pll_trim[7]
|
|
pll_trim[8] |pll_trim[8]
|
|
pll_trim[9] |pll_trim[9]
|
|
porb |porb
|
|
reset |reset
|
|
user_clock |user_clock
|
|
pad_flash_clk_oeb |pad_flash_clk_oeb
|
|
pad_flash_csb |pad_flash_csb
|
|
pad_flash_csb_oeb |pad_flash_csb_oeb
|
|
pad_flash_io0_di |pad_flash_io0_di
|
|
pad_flash_io0_do |pad_flash_io0_do
|
|
pad_flash_io0_ieb |pad_flash_io0_ieb
|
|
pad_flash_io0_oeb |pad_flash_io0_oeb
|
|
pad_flash_io1_di |pad_flash_io1_di
|
|
pad_flash_io1_do |pad_flash_io1_do
|
|
pad_flash_io1_ieb |pad_flash_io1_ieb
|
|
pad_flash_io1_oeb |pad_flash_io1_oeb
|
|
pll90_sel[0] |pll90_sel[0]
|
|
pll90_sel[1] |pll90_sel[1]
|
|
pll90_sel[2] |pll90_sel[2]
|
|
pll_dco_ena |pll_dco_ena
|
|
pll_div[0] |pll_div[0]
|
|
pll_div[1] |pll_div[1]
|
|
pll_div[2] |pll_div[2]
|
|
pll_div[3] |pll_div[3]
|
|
pll_div[4] |pll_div[4]
|
|
pll_ena |pll_ena
|
|
pll_sel[0] |pll_sel[0]
|
|
pll_sel[1] |pll_sel[1]
|
|
pll_sel[2] |pll_sel[2]
|
|
pll_trim[0] |pll_trim[0]
|
|
pll_trim[10] |pll_trim[10]
|
|
pll_trim[11] |pll_trim[11]
|
|
pll_trim[12] |pll_trim[12]
|
|
mask_rev_in[5] |mask_rev_in[5]
|
|
mask_rev_in[6] |mask_rev_in[6]
|
|
mask_rev_in[7] |mask_rev_in[7]
|
|
mask_rev_in[8] |mask_rev_in[8]
|
|
mask_rev_in[9] |mask_rev_in[9]
|
|
mask_rev_in[0] |mask_rev_in[0]
|
|
wb_clk_i |wb_clk_i
|
|
mask_rev_in[10] |mask_rev_in[10]
|
|
mask_rev_in[11] |mask_rev_in[11]
|
|
pwr_ctrl_out[0] |pwr_ctrl_out[0]
|
|
pwr_ctrl_out[1] |pwr_ctrl_out[1]
|
|
pwr_ctrl_out[2] |pwr_ctrl_out[2]
|
|
pwr_ctrl_out[3] |pwr_ctrl_out[3]
|
|
mask_rev_in[12] |mask_rev_in[12]
|
|
mask_rev_in[13] |mask_rev_in[13]
|
|
pll_bypass |pll_bypass
|
|
mask_rev_in[14] |mask_rev_in[14]
|
|
mask_rev_in[15] |mask_rev_in[15]
|
|
mask_rev_in[16] |mask_rev_in[16]
|
|
mask_rev_in[17] |mask_rev_in[17]
|
|
mask_rev_in[18] |mask_rev_in[18]
|
|
mask_rev_in[19] |mask_rev_in[19]
|
|
mask_rev_in[1] |mask_rev_in[1]
|
|
mask_rev_in[20] |mask_rev_in[20]
|
|
mask_rev_in[21] |mask_rev_in[21]
|
|
mask_rev_in[22] |mask_rev_in[22]
|
|
mask_rev_in[23] |mask_rev_in[23]
|
|
mask_rev_in[24] |mask_rev_in[24]
|
|
mask_rev_in[25] |mask_rev_in[25]
|
|
mask_rev_in[26] |mask_rev_in[26]
|
|
mask_rev_in[27] |mask_rev_in[27]
|
|
mask_rev_in[28] |mask_rev_in[28]
|
|
mask_rev_in[29] |mask_rev_in[29]
|
|
mask_rev_in[2] |mask_rev_in[2]
|
|
mask_rev_in[30] |mask_rev_in[30]
|
|
mask_rev_in[31] |mask_rev_in[31]
|
|
pll_trim[19] |pll_trim[19]
|
|
mask_rev_in[3] |mask_rev_in[3]
|
|
pll_trim[20] |pll_trim[20]
|
|
pll_trim[21] |pll_trim[21]
|
|
wb_rstn_i |wb_rstn_i
|
|
pll_trim[22] |pll_trim[22]
|
|
pll_trim[23] |pll_trim[23]
|
|
pll_trim[24] |pll_trim[24]
|
|
pll_trim[25] |pll_trim[25]
|
|
mask_rev_in[4] |mask_rev_in[4]
|
|
mgmt_gpio_in[9] |mgmt_gpio_in[9]
|
|
mgmt_gpio_in[11] |mgmt_gpio_in[11]
|
|
mgmt_gpio_in[12] |mgmt_gpio_in[12]
|
|
mgmt_gpio_in[13] |mgmt_gpio_in[13]
|
|
mgmt_gpio_in[14] |mgmt_gpio_in[14]
|
|
mgmt_gpio_in[15] |mgmt_gpio_in[15]
|
|
mgmt_gpio_in[16] |mgmt_gpio_in[16]
|
|
mgmt_gpio_in[17] |mgmt_gpio_in[17]
|
|
mgmt_gpio_in[18] |mgmt_gpio_in[18]
|
|
mgmt_gpio_in[19] |mgmt_gpio_in[19]
|
|
mgmt_gpio_in[10] |mgmt_gpio_in[10]
|
|
mgmt_gpio_oeb[10] |mgmt_gpio_oeb[10]
|
|
mgmt_gpio_oeb[11] |mgmt_gpio_oeb[11]
|
|
mgmt_gpio_oeb[12] |mgmt_gpio_oeb[12]
|
|
mgmt_gpio_oeb[13] |mgmt_gpio_oeb[13]
|
|
mgmt_gpio_oeb[14] |mgmt_gpio_oeb[14]
|
|
mgmt_gpio_oeb[15] |mgmt_gpio_oeb[15]
|
|
mgmt_gpio_oeb[16] |mgmt_gpio_oeb[16]
|
|
mgmt_gpio_oeb[17] |mgmt_gpio_oeb[17]
|
|
mgmt_gpio_oeb[18] |mgmt_gpio_oeb[18]
|
|
mgmt_gpio_oeb[19] |mgmt_gpio_oeb[19]
|
|
mgmt_gpio_oeb[9] |mgmt_gpio_oeb[9]
|
|
mgmt_gpio_out[10] |mgmt_gpio_out[10]
|
|
mgmt_gpio_out[11] |mgmt_gpio_out[11]
|
|
mgmt_gpio_out[12] |mgmt_gpio_out[12]
|
|
mgmt_gpio_out[13] |mgmt_gpio_out[13]
|
|
mgmt_gpio_out[14] |mgmt_gpio_out[14]
|
|
mgmt_gpio_out[15] |mgmt_gpio_out[15]
|
|
mgmt_gpio_out[16] |mgmt_gpio_out[16]
|
|
mgmt_gpio_out[17] |mgmt_gpio_out[17]
|
|
mgmt_gpio_out[18] |mgmt_gpio_out[18]
|
|
mgmt_gpio_out[19] |mgmt_gpio_out[19]
|
|
mgmt_gpio_out[9] |mgmt_gpio_out[9]
|
|
spimemio_flash_clk |spimemio_flash_clk
|
|
spimemio_flash_csb |spimemio_flash_csb
|
|
spimemio_flash_io0_di |spimemio_flash_io0_di
|
|
spimemio_flash_io0_do |spimemio_flash_io0_do
|
|
spimemio_flash_io0_oeb |spimemio_flash_io0_oeb
|
|
spimemio_flash_io1_di |spimemio_flash_io1_di
|
|
spimemio_flash_io1_do |spimemio_flash_io1_do
|
|
spimemio_flash_io1_oeb |spimemio_flash_io1_oeb
|
|
spimemio_flash_io2_di |spimemio_flash_io2_di
|
|
spimemio_flash_io2_do |spimemio_flash_io2_do
|
|
spimemio_flash_io2_oeb |spimemio_flash_io2_oeb
|
|
spimemio_flash_io3_di |spimemio_flash_io3_di
|
|
spimemio_flash_io3_do |spimemio_flash_io3_do
|
|
spimemio_flash_io3_oeb |spimemio_flash_io3_oeb
|
|
wb_dat_o[13] |wb_dat_o[13]
|
|
wb_dat_o[14] |wb_dat_o[14]
|
|
wb_dat_o[15] |wb_dat_o[15]
|
|
wb_dat_o[16] |wb_dat_o[16]
|
|
wb_dat_o[17] |wb_dat_o[17]
|
|
wb_dat_o[18] |wb_dat_o[18]
|
|
wb_dat_o[19] |wb_dat_o[19]
|
|
wb_dat_o[20] |wb_dat_o[20]
|
|
wb_dat_o[21] |wb_dat_o[21]
|
|
wb_dat_o[22] |wb_dat_o[22]
|
|
wb_dat_o[23] |wb_dat_o[23]
|
|
wb_dat_o[24] |wb_dat_o[24]
|
|
wb_dat_o[25] |wb_dat_o[25]
|
|
wb_dat_o[26] |wb_dat_o[26]
|
|
wb_dat_o[27] |wb_dat_o[27]
|
|
wb_dat_o[28] |wb_dat_o[28]
|
|
wb_dat_o[29] |wb_dat_o[29]
|
|
wb_dat_o[30] |wb_dat_o[30]
|
|
wb_dat_o[31] |wb_dat_o[31]
|
|
wb_dat_o[0] |wb_dat_o[0]
|
|
wb_dat_o[10] |wb_dat_o[10]
|
|
wb_dat_o[11] |wb_dat_o[11]
|
|
wb_dat_o[12] |wb_dat_o[12]
|
|
spi_sdo |spi_sdo
|
|
spi_sdoenb |spi_sdoenb
|
|
irq[1] |irq[1]
|
|
irq[2] |irq[2]
|
|
debug_in |debug_in
|
|
debug_mode |debug_mode
|
|
debug_oeb |debug_oeb
|
|
wb_dat_o[1] |wb_dat_o[1]
|
|
debug_out |debug_out
|
|
irq[0] |irq[0]
|
|
qspi_enabled |qspi_enabled
|
|
ser_rx |ser_rx
|
|
ser_tx |ser_tx
|
|
spi_csb |spi_csb
|
|
spi_enabled |spi_enabled
|
|
spi_sck |spi_sck
|
|
spi_sdi |spi_sdi
|
|
trap |trap
|
|
wb_dat_o[2] |wb_dat_o[2]
|
|
uart_enabled |uart_enabled
|
|
wb_ack_o |wb_ack_o
|
|
wb_dat_o[3] |wb_dat_o[3]
|
|
wb_dat_o[4] |wb_dat_o[4]
|
|
wb_dat_o[5] |wb_dat_o[5]
|
|
wb_dat_o[6] |wb_dat_o[6]
|
|
wb_dat_o[7] |wb_dat_o[7]
|
|
wb_dat_o[8] |wb_dat_o[8]
|
|
wb_dat_o[9] |wb_dat_o[9]
|
|
wb_stb_i |wb_stb_i
|
|
mgmt_gpio_oeb[3] |mgmt_gpio_oeb[3]
|
|
mgmt_gpio_oeb[4] |mgmt_gpio_oeb[4]
|
|
mgmt_gpio_oeb[5] |mgmt_gpio_oeb[5]
|
|
serial_clock |serial_clock
|
|
serial_data_1 |serial_data_1
|
|
serial_data_2 |serial_data_2
|
|
serial_load |serial_load
|
|
serial_resetn |serial_resetn
|
|
mgmt_gpio_oeb[6] |mgmt_gpio_oeb[6]
|
|
mgmt_gpio_oeb[7] |mgmt_gpio_oeb[7]
|
|
mgmt_gpio_oeb[8] |mgmt_gpio_oeb[8]
|
|
mgmt_gpio_in[1] |mgmt_gpio_in[1]
|
|
mgmt_gpio_out[0] |mgmt_gpio_out[0]
|
|
mgmt_gpio_in[2] |mgmt_gpio_in[2]
|
|
mgmt_gpio_in[3] |mgmt_gpio_in[3]
|
|
mgmt_gpio_in[4] |mgmt_gpio_in[4]
|
|
mgmt_gpio_in[5] |mgmt_gpio_in[5]
|
|
mgmt_gpio_in[6] |mgmt_gpio_in[6]
|
|
mgmt_gpio_in[7] |mgmt_gpio_in[7]
|
|
mgmt_gpio_in[8] |mgmt_gpio_in[8]
|
|
mgmt_gpio_in[0] |mgmt_gpio_in[0]
|
|
mgmt_gpio_oeb[0] |mgmt_gpio_oeb[0]
|
|
mgmt_gpio_oeb[1] |mgmt_gpio_oeb[1]
|
|
mgmt_gpio_out[1] |mgmt_gpio_out[1]
|
|
mgmt_gpio_out[2] |mgmt_gpio_out[2]
|
|
mgmt_gpio_out[3] |mgmt_gpio_out[3]
|
|
mgmt_gpio_out[4] |mgmt_gpio_out[4]
|
|
mgmt_gpio_out[5] |mgmt_gpio_out[5]
|
|
mgmt_gpio_out[6] |mgmt_gpio_out[6]
|
|
mgmt_gpio_out[7] |mgmt_gpio_out[7]
|
|
mgmt_gpio_out[8] |mgmt_gpio_out[8]
|
|
mgmt_gpio_oeb[2] |mgmt_gpio_oeb[2]
|
|
VPWR |VPWR
|
|
VGND |VGND
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes housekeeping_alt and housekeeping_alt are equivalent.
|
|
|
|
Circuit 2 cell mgmt_protect_hv is a black box; will not flatten Circuit 1
|
|
Warning: Equate pins: cell mgmt_protect_hv is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mgmt_protect_hv |Circuit 2: mgmt_protect_hv
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd |vccd
|
|
vdda1 |vdda1
|
|
vdda2 |vdda2
|
|
mprj2_vdd_logic1 |mprj2_vdd_logic1
|
|
mprj_vdd_logic1 |mprj_vdd_logic1
|
|
vssa1 |vssa1
|
|
vssd |vssd
|
|
vssa2 |vssa2
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mgmt_protect_hv and mgmt_protect_hv are equivalent.
|
|
|
|
Class sky130_fd_sc_hd__and2b_4 (0): Merged 6 parallel devices.
|
|
Class sky130_fd_sc_hd__and2b_4 (1): Merged 6 parallel devices.
|
|
Subcircuit summary:
|
|
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_fd_pr__nfet_01v8 (7->4) |sky130_fd_pr__nfet_01v8 (7->4)
|
|
sky130_fd_pr__pfet_01v8_hvt (7->4) |sky130_fd_pr__pfet_01v8_hvt (7->4)
|
|
Number of devices: 8 |Number of devices: 8
|
|
Number of nets: 10 |Number of nets: 10
|
|
---------------------------------------------------------------------------------------
|
|
Netlists match uniquely.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: sky130_fd_sc_hd__and2b_4 |Circuit 2: sky130_fd_sc_hd__and2b_4
|
|
-------------------------------------------|-------------------------------------------
|
|
VPWR |VPWR
|
|
VPB |VPB
|
|
VNB |VNB
|
|
VGND |VGND
|
|
A_N |A_N
|
|
X |X
|
|
B |B
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes sky130_fd_sc_hd__and2b_4 and sky130_fd_sc_hd__and2b_4 are equivalent.
|
|
|
|
Circuit 2 cell mprj_logic_high is a black box; will not flatten Circuit 1
|
|
Class mprj_logic_high (0): Merged 141 parallel devices.
|
|
Warning: Equate pins: cell mprj_logic_high is a placeholder, treated as a black box.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: mprj_logic_high |Circuit 2: mprj_logic_high
|
|
-------------------------------------------|-------------------------------------------
|
|
HI[212] |HI[212]
|
|
HI[406] |HI[406]
|
|
HI[173] |HI[173]
|
|
HI[175] |HI[175]
|
|
HI[184] |HI[184]
|
|
HI[194] |HI[194]
|
|
HI[1] |HI[1]
|
|
HI[20] |HI[20]
|
|
HI[225] |HI[225]
|
|
HI[238] |HI[238]
|
|
HI[239] |HI[239]
|
|
HI[249] |HI[249]
|
|
HI[307] |HI[307]
|
|
HI[308] |HI[308]
|
|
HI[331] |HI[331]
|
|
HI[337] |HI[337]
|
|
HI[341] |HI[341]
|
|
HI[343] |HI[343]
|
|
HI[462] |HI[462]
|
|
HI[46] |HI[46]
|
|
HI[47] |HI[47]
|
|
HI[48] |HI[48]
|
|
HI[49] |HI[49]
|
|
HI[4] |HI[4]
|
|
HI[50] |HI[50]
|
|
HI[51] |HI[51]
|
|
HI[52] |HI[52]
|
|
HI[53] |HI[53]
|
|
HI[54] |HI[54]
|
|
HI[55] |HI[55]
|
|
HI[56] |HI[56]
|
|
HI[57] |HI[57]
|
|
HI[58] |HI[58]
|
|
HI[59] |HI[59]
|
|
HI[5] |HI[5]
|
|
HI[60] |HI[60]
|
|
HI[61] |HI[61]
|
|
HI[62] |HI[62]
|
|
HI[63] |HI[63]
|
|
HI[64] |HI[64]
|
|
HI[65] |HI[65]
|
|
HI[66] |HI[66]
|
|
HI[67] |HI[67]
|
|
HI[68] |HI[68]
|
|
HI[69] |HI[69]
|
|
HI[6] |HI[6]
|
|
HI[70] |HI[70]
|
|
HI[71] |HI[71]
|
|
HI[72] |HI[72]
|
|
HI[73] |HI[73]
|
|
HI[74] |HI[74]
|
|
HI[75] |HI[75]
|
|
HI[76] |HI[76]
|
|
HI[77] |HI[77]
|
|
HI[78] |HI[78]
|
|
HI[79] |HI[79]
|
|
HI[7] |HI[7]
|
|
HI[80] |HI[80]
|
|
HI[81] |HI[81]
|
|
HI[82] |HI[82]
|
|
HI[83] |HI[83]
|
|
HI[84] |HI[84]
|
|
HI[85] |HI[85]
|
|
HI[86] |HI[86]
|
|
HI[87] |HI[87]
|
|
HI[88] |HI[88]
|
|
HI[89] |HI[89]
|
|
HI[8] |HI[8]
|
|
HI[90] |HI[90]
|
|
HI[91] |HI[91]
|
|
HI[92] |HI[92]
|
|
HI[93] |HI[93]
|
|
HI[94] |HI[94]
|
|
HI[95] |HI[95]
|
|
HI[96] |HI[96]
|
|
HI[97] |HI[97]
|
|
HI[98] |HI[98]
|
|
HI[99] |HI[99]
|
|
HI[9] |HI[9]
|
|
vccd1 |vccd1
|
|
HI[437] |HI[437]
|
|
HI[438] |HI[438]
|
|
HI[439] |HI[439]
|
|
HI[43] |HI[43]
|
|
HI[440] |HI[440]
|
|
HI[441] |HI[441]
|
|
HI[442] |HI[442]
|
|
HI[443] |HI[443]
|
|
HI[444] |HI[444]
|
|
HI[445] |HI[445]
|
|
HI[446] |HI[446]
|
|
HI[447] |HI[447]
|
|
HI[448] |HI[448]
|
|
HI[449] |HI[449]
|
|
HI[44] |HI[44]
|
|
HI[450] |HI[450]
|
|
HI[451] |HI[451]
|
|
HI[452] |HI[452]
|
|
HI[453] |HI[453]
|
|
HI[454] |HI[454]
|
|
HI[455] |HI[455]
|
|
HI[456] |HI[456]
|
|
HI[457] |HI[457]
|
|
HI[458] |HI[458]
|
|
HI[459] |HI[459]
|
|
HI[45] |HI[45]
|
|
HI[460] |HI[460]
|
|
HI[461] |HI[461]
|
|
HI[434] |HI[434]
|
|
HI[435] |HI[435]
|
|
HI[436] |HI[436]
|
|
HI[416] |HI[416]
|
|
HI[417] |HI[417]
|
|
HI[418] |HI[418]
|
|
HI[419] |HI[419]
|
|
HI[41] |HI[41]
|
|
HI[420] |HI[420]
|
|
HI[421] |HI[421]
|
|
HI[422] |HI[422]
|
|
HI[423] |HI[423]
|
|
HI[424] |HI[424]
|
|
HI[425] |HI[425]
|
|
HI[426] |HI[426]
|
|
HI[427] |HI[427]
|
|
HI[428] |HI[428]
|
|
HI[429] |HI[429]
|
|
HI[42] |HI[42]
|
|
HI[430] |HI[430]
|
|
HI[431] |HI[431]
|
|
HI[432] |HI[432]
|
|
HI[433] |HI[433]
|
|
HI[40] |HI[40]
|
|
HI[410] |HI[410]
|
|
HI[411] |HI[411]
|
|
HI[412] |HI[412]
|
|
HI[413] |HI[413]
|
|
HI[407] |HI[407]
|
|
HI[408] |HI[408]
|
|
HI[414] |HI[414]
|
|
HI[415] |HI[415]
|
|
HI[409] |HI[409]
|
|
HI[232] |HI[232]
|
|
HI[234] |HI[234]
|
|
HI[237] |HI[237]
|
|
HI[23] |HI[23]
|
|
HI[242] |HI[242]
|
|
HI[245] |HI[245]
|
|
HI[248] |HI[248]
|
|
HI[250] |HI[250]
|
|
HI[253] |HI[253]
|
|
HI[256] |HI[256]
|
|
HI[259] |HI[259]
|
|
HI[261] |HI[261]
|
|
HI[269] |HI[269]
|
|
HI[272] |HI[272]
|
|
HI[276] |HI[276]
|
|
HI[27] |HI[27]
|
|
HI[283] |HI[283]
|
|
HI[287] |HI[287]
|
|
HI[290] |HI[290]
|
|
HI[294] |HI[294]
|
|
HI[298] |HI[298]
|
|
HI[300] |HI[300]
|
|
HI[304] |HI[304]
|
|
HI[215] |HI[215]
|
|
HI[218] |HI[218]
|
|
HI[220] |HI[220]
|
|
HI[223] |HI[223]
|
|
HI[226] |HI[226]
|
|
HI[229] |HI[229]
|
|
HI[231] |HI[231]
|
|
HI[295] |HI[295]
|
|
HI[203] |HI[203]
|
|
HI[187] |HI[187]
|
|
HI[301] |HI[301]
|
|
HI[275] |HI[275]
|
|
HI[306] |HI[306]
|
|
HI[207] |HI[207]
|
|
HI[191] |HI[191]
|
|
HI[309] |HI[309]
|
|
HI[311] |HI[311]
|
|
HI[313] |HI[313]
|
|
HI[314] |HI[314]
|
|
HI[315] |HI[315]
|
|
HI[319] |HI[319]
|
|
HI[322] |HI[322]
|
|
HI[323] |HI[323]
|
|
HI[326] |HI[326]
|
|
HI[32] |HI[32]
|
|
HI[211] |HI[211]
|
|
HI[333] |HI[333]
|
|
HI[167] |HI[167]
|
|
HI[233] |HI[233]
|
|
HI[342] |HI[342]
|
|
HI[216] |HI[216]
|
|
HI[170] |HI[170]
|
|
HI[21] |HI[21]
|
|
HI[281] |HI[281]
|
|
HI[180] |HI[180]
|
|
HI[199] |HI[199]
|
|
HI[265] |HI[265]
|
|
HI[268] |HI[268]
|
|
HI[382] |HI[382]
|
|
HI[383] |HI[383]
|
|
HI[384] |HI[384]
|
|
HI[385] |HI[385]
|
|
HI[386] |HI[386]
|
|
HI[387] |HI[387]
|
|
HI[388] |HI[388]
|
|
HI[389] |HI[389]
|
|
HI[38] |HI[38]
|
|
HI[390] |HI[390]
|
|
HI[391] |HI[391]
|
|
HI[392] |HI[392]
|
|
HI[393] |HI[393]
|
|
HI[394] |HI[394]
|
|
HI[395] |HI[395]
|
|
HI[396] |HI[396]
|
|
HI[397] |HI[397]
|
|
HI[398] |HI[398]
|
|
HI[399] |HI[399]
|
|
HI[39] |HI[39]
|
|
HI[3] |HI[3]
|
|
HI[400] |HI[400]
|
|
HI[401] |HI[401]
|
|
HI[402] |HI[402]
|
|
HI[403] |HI[403]
|
|
HI[404] |HI[404]
|
|
HI[405] |HI[405]
|
|
HI[37] |HI[37]
|
|
HI[380] |HI[380]
|
|
HI[381] |HI[381]
|
|
HI[353] |HI[353]
|
|
HI[354] |HI[354]
|
|
HI[355] |HI[355]
|
|
HI[356] |HI[356]
|
|
HI[357] |HI[357]
|
|
HI[358] |HI[358]
|
|
HI[359] |HI[359]
|
|
HI[35] |HI[35]
|
|
HI[360] |HI[360]
|
|
HI[361] |HI[361]
|
|
HI[362] |HI[362]
|
|
HI[363] |HI[363]
|
|
HI[364] |HI[364]
|
|
HI[365] |HI[365]
|
|
HI[366] |HI[366]
|
|
HI[367] |HI[367]
|
|
HI[368] |HI[368]
|
|
HI[369] |HI[369]
|
|
HI[36] |HI[36]
|
|
HI[370] |HI[370]
|
|
HI[371] |HI[371]
|
|
HI[372] |HI[372]
|
|
HI[373] |HI[373]
|
|
HI[374] |HI[374]
|
|
HI[375] |HI[375]
|
|
HI[376] |HI[376]
|
|
HI[377] |HI[377]
|
|
HI[378] |HI[378]
|
|
HI[379] |HI[379]
|
|
HI[351] |HI[351]
|
|
HI[352] |HI[352]
|
|
HI[302] |HI[302]
|
|
HI[317] |HI[317]
|
|
HI[318] |HI[318]
|
|
HI[176] |HI[176]
|
|
HI[332] |HI[332]
|
|
HI[181] |HI[181]
|
|
HI[198] |HI[198]
|
|
HI[202] |HI[202]
|
|
HI[205] |HI[205]
|
|
HI[208] |HI[208]
|
|
HI[213] |HI[213]
|
|
HI[217] |HI[217]
|
|
HI[219] |HI[219]
|
|
HI[224] |HI[224]
|
|
HI[235] |HI[235]
|
|
HI[236] |HI[236]
|
|
HI[244] |HI[244]
|
|
HI[263] |HI[263]
|
|
HI[267] |HI[267]
|
|
HI[270] |HI[270]
|
|
HI[274] |HI[274]
|
|
HI[278] |HI[278]
|
|
HI[285] |HI[285]
|
|
HI[292] |HI[292]
|
|
HI[338] |HI[338]
|
|
HI[339] |HI[339]
|
|
HI[165] |HI[165]
|
|
HI[29] |HI[29]
|
|
HI[328] |HI[328]
|
|
HI[227] |HI[227]
|
|
HI[172] |HI[172]
|
|
HI[334] |HI[334]
|
|
HI[186] |HI[186]
|
|
HI[240] |HI[240]
|
|
HI[189] |HI[189]
|
|
HI[246] |HI[246]
|
|
HI[24] |HI[24]
|
|
HI[251] |HI[251]
|
|
HI[305] |HI[305]
|
|
HI[257] |HI[257]
|
|
HI[197] |HI[197]
|
|
HI[266] |HI[266]
|
|
HI[16] |HI[16]
|
|
HI[19] |HI[19]
|
|
HI[201] |HI[201]
|
|
HI[320] |HI[320]
|
|
HI[279] |HI[279]
|
|
HI[204] |HI[204]
|
|
HI[286] |HI[286]
|
|
HI[289] |HI[289]
|
|
HI[33] |HI[33]
|
|
HI[183] |HI[183]
|
|
HI[30] |HI[30]
|
|
HI[296] |HI[296]
|
|
HI[164] |HI[164]
|
|
HI[324] |HI[324]
|
|
HI[299] |HI[299]
|
|
HI[178] |HI[178]
|
|
HI[344] |HI[344]
|
|
HI[345] |HI[345]
|
|
HI[346] |HI[346]
|
|
HI[123] |HI[123]
|
|
HI[347] |HI[347]
|
|
HI[348] |HI[348]
|
|
HI[124] |HI[124]
|
|
HI[349] |HI[349]
|
|
HI[34] |HI[34]
|
|
HI[125] |HI[125]
|
|
HI[350] |HI[350]
|
|
HI[126] |HI[126]
|
|
HI[127] |HI[127]
|
|
HI[128] |HI[128]
|
|
HI[117] |HI[117]
|
|
HI[129] |HI[129]
|
|
HI[130] |HI[130]
|
|
HI[131] |HI[131]
|
|
HI[134] |HI[134]
|
|
HI[135] |HI[135]
|
|
HI[115] |HI[115]
|
|
HI[136] |HI[136]
|
|
HI[13] |HI[13]
|
|
HI[114] |HI[114]
|
|
HI[118] |HI[118]
|
|
HI[116] |HI[116]
|
|
HI[15] |HI[15]
|
|
HI[119] |HI[119]
|
|
HI[11] |HI[11]
|
|
HI[121] |HI[121]
|
|
HI[120] |HI[120]
|
|
HI[140] |HI[140]
|
|
HI[141] |HI[141]
|
|
HI[142] |HI[142]
|
|
HI[143] |HI[143]
|
|
HI[144] |HI[144]
|
|
HI[145] |HI[145]
|
|
HI[146] |HI[146]
|
|
HI[147] |HI[147]
|
|
HI[148] |HI[148]
|
|
HI[149] |HI[149]
|
|
HI[14] |HI[14]
|
|
HI[150] |HI[150]
|
|
HI[151] |HI[151]
|
|
HI[152] |HI[152]
|
|
HI[132] |HI[132]
|
|
HI[153] |HI[153]
|
|
HI[154] |HI[154]
|
|
HI[155] |HI[155]
|
|
HI[156] |HI[156]
|
|
HI[157] |HI[157]
|
|
HI[133] |HI[133]
|
|
HI[158] |HI[158]
|
|
HI[159] |HI[159]
|
|
HI[137] |HI[137]
|
|
HI[160] |HI[160]
|
|
HI[161] |HI[161]
|
|
HI[162] |HI[162]
|
|
HI[138] |HI[138]
|
|
HI[139] |HI[139]
|
|
HI[122] |HI[122]
|
|
HI[12] |HI[12]
|
|
HI[177] |HI[177]
|
|
HI[327] |HI[327]
|
|
HI[221] |HI[221]
|
|
HI[26] |HI[26]
|
|
HI[271] |HI[271]
|
|
HI[222] |HI[222]
|
|
HI[206] |HI[206]
|
|
HI[329] |HI[329]
|
|
HI[277] |HI[277]
|
|
HI[321] |HI[321]
|
|
HI[179] |HI[179]
|
|
HI[280] |HI[280]
|
|
HI[330] |HI[330]
|
|
HI[282] |HI[282]
|
|
HI[31] |HI[31]
|
|
HI[284] |HI[284]
|
|
HI[168] |HI[168]
|
|
HI[210] |HI[210]
|
|
HI[288] |HI[288]
|
|
HI[28] |HI[28]
|
|
HI[17] |HI[17]
|
|
HI[291] |HI[291]
|
|
HI[185] |HI[185]
|
|
HI[214] |HI[214]
|
|
HI[260] |HI[260]
|
|
HI[228] |HI[228]
|
|
HI[297] |HI[297]
|
|
HI[262] |HI[262]
|
|
HI[18] |HI[18]
|
|
HI[209] |HI[209]
|
|
HI[2] |HI[2]
|
|
HI[258] |HI[258]
|
|
HI[174] |HI[174]
|
|
HI[325] |HI[325]
|
|
HI[25] |HI[25]
|
|
HI[171] |HI[171]
|
|
HI[247] |HI[247]
|
|
HI[230] |HI[230]
|
|
HI[312] |HI[312]
|
|
HI[264] |HI[264]
|
|
HI[193] |HI[193]
|
|
HI[195] |HI[195]
|
|
HI[340] |HI[340]
|
|
HI[166] |HI[166]
|
|
HI[303] |HI[303]
|
|
HI[241] |HI[241]
|
|
HI[293] |HI[293]
|
|
HI[335] |HI[335]
|
|
HI[163] |HI[163]
|
|
HI[200] |HI[200]
|
|
HI[182] |HI[182]
|
|
HI[254] |HI[254]
|
|
HI[188] |HI[188]
|
|
HI[273] |HI[273]
|
|
HI[169] |HI[169]
|
|
HI[336] |HI[336]
|
|
HI[190] |HI[190]
|
|
HI[243] |HI[243]
|
|
HI[196] |HI[196]
|
|
HI[0] |HI[0]
|
|
HI[100] |HI[100]
|
|
HI[101] |HI[101]
|
|
HI[102] |HI[102]
|
|
HI[103] |HI[103]
|
|
HI[104] |HI[104]
|
|
HI[105] |HI[105]
|
|
HI[106] |HI[106]
|
|
HI[107] |HI[107]
|
|
HI[108] |HI[108]
|
|
HI[109] |HI[109]
|
|
HI[10] |HI[10]
|
|
HI[110] |HI[110]
|
|
HI[111] |HI[111]
|
|
HI[112] |HI[112]
|
|
HI[113] |HI[113]
|
|
HI[192] |HI[192]
|
|
HI[316] |HI[316]
|
|
HI[255] |HI[255]
|
|
HI[22] |HI[22]
|
|
HI[252] |HI[252]
|
|
HI[310] |HI[310]
|
|
vssd1 |vssd1
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes mprj_logic_high and mprj_logic_high are equivalent.
|
|
Flattening unmatched subcell sky130_fd_sc_hd__tapvpwrvgnd_1 in circuit caravel_core (1)(28782 instances)
|
|
Flattening unmatched subcell sky130_fd_sc_hd__fill_1 in circuit caravel_core (1)(3753 instances)
|
|
Flattening unmatched subcell sky130_fd_sc_hd__fill_2 in circuit caravel_core (1)(1728 instances)
|
|
|
|
Cell caravel_core (0) disconnected node: vssd1_uq0
|
|
Class caravel_core (0): Merged 112748 parallel devices.
|
|
Class caravel_core (1): Merged 112748 parallel devices.
|
|
Cell caravel_core (0) disconnected node: vssd1_uq0
|
|
Subcircuit summary:
|
|
Circuit 1: caravel_core |Circuit 2: caravel_core
|
|
-------------------------------------------|-------------------------------------------
|
|
sky130_ef_sc_hd__decap_12 (66277->1) |sky130_ef_sc_hd__decap_12 (66277->1)
|
|
sky130_fd_sc_hd__decap_6 (19596->1) |sky130_fd_sc_hd__decap_6 (19596->1)
|
|
sky130_fd_sc_hd__diode_2 (12905->3286) |sky130_fd_sc_hd__diode_2 (12905->3286)
|
|
sky130_fd_sc_hd__nand2b_1 (506) |sky130_fd_sc_hd__nand2b_1 (506)
|
|
sky130_fd_sc_hd__decap_3 (6712->1) |sky130_fd_sc_hd__decap_3 (6712->1)
|
|
sky130_fd_sc_hd__decap_8 (7807->1) |sky130_fd_sc_hd__decap_8 (7807->1)
|
|
sky130_fd_sc_hd__and2_4 (292) |sky130_fd_sc_hd__and2_4 (292)
|
|
sky130_fd_sc_hd__or2_1 (494) |sky130_fd_sc_hd__or2_1 (494)
|
|
sky130_fd_sc_hd__buf_1 (245) |sky130_fd_sc_hd__buf_1 (245)
|
|
sky130_fd_sc_hd__clkbuf_2 (154) |sky130_fd_sc_hd__clkbuf_2 (154)
|
|
sky130_fd_sc_hd__decap_4 (2742->1) |sky130_fd_sc_hd__decap_4 (2742->1)
|
|
sky130_fd_sc_hd__buf_8 (62) |sky130_fd_sc_hd__buf_8 (62)
|
|
sky130_fd_sc_hd__dfbbn_2 (482) |sky130_fd_sc_hd__dfbbn_2 (482)
|
|
sky130_fd_sc_hd__dfrtp_1 (505) |sky130_fd_sc_hd__dfrtp_1 (505)
|
|
sky130_fd_sc_hd__clkbuf_1 (10) |sky130_fd_sc_hd__clkbuf_1 (10)
|
|
sky130_fd_sc_hd__buf_4 (69) |sky130_fd_sc_hd__buf_4 (69)
|
|
sky130_fd_sc_hd__clkbuf_16 (566) |sky130_fd_sc_hd__clkbuf_16 (566)
|
|
sky130_fd_sc_hd__nand2b_2 (20) |sky130_fd_sc_hd__nand2b_2 (20)
|
|
sky130_fd_sc_hd__inv_2 (530) |sky130_fd_sc_hd__inv_2 (530)
|
|
sky130_fd_sc_hd__and2_2 (55) |sky130_fd_sc_hd__and2_2 (55)
|
|
sky130_fd_sc_hd__clkbuf_8 (61) |sky130_fd_sc_hd__clkbuf_8 (61)
|
|
sky130_fd_sc_hd__clkbuf_4 (64) |sky130_fd_sc_hd__clkbuf_4 (64)
|
|
gpio_logic_high (38) |gpio_logic_high (38)
|
|
sky130_fd_sc_hd__inv_4 (98) |sky130_fd_sc_hd__inv_4 (98)
|
|
sky130_fd_sc_hd__conb_1 (108) |sky130_fd_sc_hd__conb_1 (108)
|
|
sky130_fd_sc_hd__and2_1 (62) |sky130_fd_sc_hd__and2_1 (62)
|
|
sky130_fd_sc_hd__buf_6 (38) |sky130_fd_sc_hd__buf_6 (38)
|
|
sky130_fd_sc_hd__buf_12 (127) |sky130_fd_sc_hd__buf_12 (127)
|
|
sky130_fd_sc_hd__clkinv_4 (33) |sky130_fd_sc_hd__clkinv_4 (33)
|
|
sky130_fd_sc_hd__mux2_4 (24) |sky130_fd_sc_hd__mux2_4 (24)
|
|
sky130_fd_sc_hd__nand2_4 (126) |sky130_fd_sc_hd__nand2_4 (126)
|
|
sky130_fd_sc_hd__clkinv_8 (29) |sky130_fd_sc_hd__clkinv_8 (29)
|
|
sky130_fd_sc_hd__mux2_1 (115) |sky130_fd_sc_hd__mux2_1 (115)
|
|
sky130_fd_sc_hd__buf_2 (74) |sky130_fd_sc_hd__buf_2 (74)
|
|
sky130_fd_sc_hd__and3b_4 (128) |sky130_fd_sc_hd__and3b_4 (128)
|
|
gpio_defaults_block (38) |gpio_defaults_block (38)
|
|
sky130_fd_sc_hd__nand2_8 (33) |sky130_fd_sc_hd__nand2_8 (33)
|
|
sky130_fd_sc_hd__dfrtp_2 (17) |sky130_fd_sc_hd__dfrtp_2 (17)
|
|
digital_locked_loop (1) |digital_locked_loop (1)
|
|
mgmt_core_wrapper (1) |mgmt_core_wrapper (1)
|
|
sky130_fd_sc_hd__dlymetal6s2s_1 (8) |sky130_fd_sc_hd__dlymetal6s2s_1 (8)
|
|
sky130_fd_sc_hd__dfrtp_4 (8) |sky130_fd_sc_hd__dfrtp_4 (8)
|
|
sky130_fd_sc_hd__nand2b_4 (6) |sky130_fd_sc_hd__nand2b_4 (6)
|
|
sky130_fd_sc_hd__mux2_8 (2) |sky130_fd_sc_hd__mux2_8 (2)
|
|
simple_por (1) |simple_por (1)
|
|
sky130_fd_sc_hd__dfbbn_1 (12) |sky130_fd_sc_hd__dfbbn_1 (12)
|
|
sky130_fd_sc_hd__mux2_2 (11) |sky130_fd_sc_hd__mux2_2 (11)
|
|
caravel_clocking (1) |caravel_clocking (1)
|
|
spare_logic_block (4) |spare_logic_block (4)
|
|
user_id_programming (1) |user_id_programming (1)
|
|
sky130_fd_sc_hd__nand2_2 (5) |sky130_fd_sc_hd__nand2_2 (5)
|
|
mprj2_logic_high (1) |mprj2_logic_high (1)
|
|
mprj_io_buffer (1) |mprj_io_buffer (1)
|
|
sky130_fd_sc_hd__inv_6 (4) |sky130_fd_sc_hd__inv_6 (4)
|
|
xres_buf (1) |xres_buf (1)
|
|
sky130_fd_sc_hd__dlygate4sd3_1 (1) |sky130_fd_sc_hd__dlygate4sd3_1 (1)
|
|
user_project_wrapper (1) |user_project_wrapper (1)
|
|
housekeeping_alt (1) |housekeeping_alt (1)
|
|
mgmt_protect_hv (1) |mgmt_protect_hv (1)
|
|
sky130_fd_sc_hd__and2b_4 (1) |sky130_fd_sc_hd__and2b_4 (1)
|
|
mprj_logic_high (1) |mprj_logic_high (1)
|
|
Number of devices: 8568 |Number of devices: 8568
|
|
Number of nets: 8028 |Number of nets: 8028
|
|
---------------------------------------------------------------------------------------
|
|
Resolving symmetries by property value.
|
|
Resolving symmetries by pin name.
|
|
Netlists match with 43 symmetries.
|
|
|
|
Subcircuit pins:
|
|
Circuit 1: caravel_core |Circuit 2: caravel_core
|
|
-------------------------------------------|-------------------------------------------
|
|
vccd1 |vccd1
|
|
vssd1 |vssd1
|
|
mprj_io_one[36] |mprj_io_one[36]
|
|
mprj_io_one[37] |mprj_io_one[37]
|
|
mprj_io_one[6] |mprj_io_one[6]
|
|
mprj_io_one[7] |mprj_io_one[7]
|
|
mprj_io_one[8] |mprj_io_one[8]
|
|
mprj_io_one[9] |mprj_io_one[9]
|
|
mprj_io_one[26] |mprj_io_one[26]
|
|
mprj_io_one[10] |mprj_io_one[10]
|
|
mprj_io_one[27] |mprj_io_one[27]
|
|
mprj_io_one[11] |mprj_io_one[11]
|
|
mprj_io_one[28] |mprj_io_one[28]
|
|
mprj_io_one[12] |mprj_io_one[12]
|
|
mprj_io_one[29] |mprj_io_one[29]
|
|
mprj_io_one[13] |mprj_io_one[13]
|
|
mprj_io_one[30] |mprj_io_one[30]
|
|
mprj_io_one[14] |mprj_io_one[14]
|
|
mprj_io_one[31] |mprj_io_one[31]
|
|
mprj_io_one[15] |mprj_io_one[15]
|
|
mprj_io_one[32] |mprj_io_one[32]
|
|
mprj_io_one[33] |mprj_io_one[33]
|
|
mprj_io_one[34] |mprj_io_one[34]
|
|
mprj_io_one[35] |mprj_io_one[35]
|
|
mprj_io_one[16] |mprj_io_one[16]
|
|
mprj_io_one[0] |mprj_io_one[0]
|
|
mprj_io_one[17] |mprj_io_one[17]
|
|
mprj_io_one[1] |mprj_io_one[1]
|
|
mprj_io_one[18] |mprj_io_one[18]
|
|
mprj_io_one[2] |mprj_io_one[2]
|
|
mprj_io_one[19] |mprj_io_one[19]
|
|
mprj_io_one[3] |mprj_io_one[3]
|
|
mprj_io_one[20] |mprj_io_one[20]
|
|
mprj_io_one[4] |mprj_io_one[4]
|
|
mprj_io_one[21] |mprj_io_one[21]
|
|
mprj_io_one[5] |mprj_io_one[5]
|
|
mprj_io_one[22] |mprj_io_one[22]
|
|
mprj_io_one[23] |mprj_io_one[23]
|
|
mprj_io_one[24] |mprj_io_one[24]
|
|
mprj_io_one[25] |mprj_io_one[25]
|
|
porb_h |porb_h
|
|
mprj_io_dm[59] |mprj_io_dm[59]
|
|
mprj_io_dm[68] |mprj_io_dm[68]
|
|
mprj_io_dm[20] |mprj_io_dm[20]
|
|
mprj_io_dm[103] |mprj_io_dm[103]
|
|
mprj_io_dm[14] |mprj_io_dm[14]
|
|
mprj_io_dm[17] |mprj_io_dm[17]
|
|
mprj_io_dm[98] |mprj_io_dm[98]
|
|
mprj_io_dm[49] |mprj_io_dm[49]
|
|
mprj_io_dm[67] |mprj_io_dm[67]
|
|
mprj_io_dm[76] |mprj_io_dm[76]
|
|
mprj_io_dm[56] |mprj_io_dm[56]
|
|
mprj_io_dm[38] |mprj_io_dm[38]
|
|
mprj_io_dm[44] |mprj_io_dm[44]
|
|
mprj_io_dm[74] |mprj_io_dm[74]
|
|
mprj_io_dm[53] |mprj_io_dm[53]
|
|
mprj_io_dm[62] |mprj_io_dm[62]
|
|
mprj_io_dm[71] |mprj_io_dm[71]
|
|
mprj_io_dm[23] |mprj_io_dm[23]
|
|
mprj_io_dm[26] |mprj_io_dm[26]
|
|
mprj_io_dm[29] |mprj_io_dm[29]
|
|
mprj_io_dm[32] |mprj_io_dm[32]
|
|
mprj_io_dm[35] |mprj_io_dm[35]
|
|
mprj_io_dm[41] |mprj_io_dm[41]
|
|
mprj_io_dm[65] |mprj_io_dm[65]
|
|
mprj_io_dm[77] |mprj_io_dm[77]
|
|
mprj_io_dm[80] |mprj_io_dm[80]
|
|
mprj_io_dm[83] |mprj_io_dm[83]
|
|
mprj_io_dm[86] |mprj_io_dm[86]
|
|
mprj_io_dm[89] |mprj_io_dm[89]
|
|
mprj_io_dm[92] |mprj_io_dm[92]
|
|
mprj_io_dm[95] |mprj_io_dm[95]
|
|
mprj_io_dm[37] |mprj_io_dm[37]
|
|
mprj_io_dm[43] |mprj_io_dm[43]
|
|
mprj_io_dm[70] |mprj_io_dm[70]
|
|
mprj_io_dm[73] |mprj_io_dm[73]
|
|
mprj_io_dm[104] |mprj_io_dm[104]
|
|
mprj_io_dm[50] |mprj_io_dm[50]
|
|
mprj_io_dm[22] |mprj_io_dm[22]
|
|
mprj_io_dm[25] |mprj_io_dm[25]
|
|
mprj_io_dm[28] |mprj_io_dm[28]
|
|
mprj_io_dm[31] |mprj_io_dm[31]
|
|
mprj_io_dm[34] |mprj_io_dm[34]
|
|
mprj_io_dm[40] |mprj_io_dm[40]
|
|
mprj_io_dm[52] |mprj_io_dm[52]
|
|
mprj_io_dm[55] |mprj_io_dm[55]
|
|
mprj_io_dm[58] |mprj_io_dm[58]
|
|
mprj_io_dm[61] |mprj_io_dm[61]
|
|
mprj_io_dm[64] |mprj_io_dm[64]
|
|
mprj_io_dm[79] |mprj_io_dm[79]
|
|
mprj_io_dm[82] |mprj_io_dm[82]
|
|
mprj_io_dm[85] |mprj_io_dm[85]
|
|
mprj_io_dm[88] |mprj_io_dm[88]
|
|
mprj_io_dm[91] |mprj_io_dm[91]
|
|
mprj_io_dm[94] |mprj_io_dm[94]
|
|
mprj_io_dm[96] |mprj_io_dm[96]
|
|
mprj_io_out[30] |mprj_io_out[30]
|
|
mprj_io_dm[111] |mprj_io_dm[111]
|
|
mprj_io_dm[12] |mprj_io_dm[12]
|
|
mprj_io_dm[15] |mprj_io_dm[15]
|
|
mprj_io_slow_sel[10] |mprj_io_slow_sel[10]
|
|
mprj_io_slow_sel[28] |mprj_io_slow_sel[28]
|
|
mprj_io_slow_sel[14] |mprj_io_slow_sel[14]
|
|
mprj_io_vtrip_sel[10] |mprj_io_vtrip_sel[10]
|
|
mprj_io_inp_dis[26] |mprj_io_inp_dis[26]
|
|
mprj_io_vtrip_sel[30] |mprj_io_vtrip_sel[30]
|
|
mprj_io_dm[0] |mprj_io_dm[0]
|
|
mprj_io_dm[105] |mprj_io_dm[105]
|
|
mprj_io_dm[108] |mprj_io_dm[108]
|
|
mprj_io_dm[3] |mprj_io_dm[3]
|
|
mprj_io_dm[6] |mprj_io_dm[6]
|
|
mprj_io_dm[99] |mprj_io_dm[99]
|
|
mprj_io_dm[9] |mprj_io_dm[9]
|
|
mprj_io_dm[18] |mprj_io_dm[18]
|
|
mprj_io_dm[75] |mprj_io_dm[75]
|
|
mprj_io_dm[78] |mprj_io_dm[78]
|
|
gpio_outenb_core |gpio_outenb_core
|
|
mprj_io_dm[21] |mprj_io_dm[21]
|
|
mprj_io_dm[24] |mprj_io_dm[24]
|
|
mprj_io_dm[30] |mprj_io_dm[30]
|
|
mprj_io_dm[45] |mprj_io_dm[45]
|
|
mprj_io_dm[51] |mprj_io_dm[51]
|
|
mprj_io_dm[69] |mprj_io_dm[69]
|
|
mprj_io_dm[57] |mprj_io_dm[57]
|
|
mprj_io_dm[60] |mprj_io_dm[60]
|
|
mprj_io_oeb[18] |mprj_io_oeb[18]
|
|
mprj_io_holdover[18] |mprj_io_holdover[18]
|
|
mprj_io_holdover[14] |mprj_io_holdover[14]
|
|
mprj_io_analog_pol[20] |mprj_io_analog_pol[20]
|
|
mprj_io_slow_sel[19] |mprj_io_slow_sel[19]
|
|
mprj_io_analog_sel[23] |mprj_io_analog_sel[23]
|
|
mprj_io_slow_sel[22] |mprj_io_slow_sel[22]
|
|
mprj_io_analog_pol[23] |mprj_io_analog_pol[23]
|
|
mprj_io_analog_en[21] |mprj_io_analog_en[21]
|
|
mprj_io_analog_en[22] |mprj_io_analog_en[22]
|
|
mprj_io_analog_pol[21] |mprj_io_analog_pol[21]
|
|
mprj_io_analog_sel[21] |mprj_io_analog_sel[21]
|
|
mprj_io_analog_sel[22] |mprj_io_analog_sel[22]
|
|
mprj_io_ib_mode_sel[21] |mprj_io_ib_mode_sel[21]
|
|
mprj_io_ib_mode_sel[23] |mprj_io_ib_mode_sel[23]
|
|
mprj_io_inp_dis[21] |mprj_io_inp_dis[21]
|
|
mprj_io_slow_sel[21] |mprj_io_slow_sel[21]
|
|
mprj_io_oeb[16] |mprj_io_oeb[16]
|
|
mprj_io_oeb[15] |mprj_io_oeb[15]
|
|
mprj_io_oeb[17] |mprj_io_oeb[17]
|
|
mprj_io_oeb[26] |mprj_io_oeb[26]
|
|
mprj_io_oeb[34] |mprj_io_oeb[34]
|
|
mprj_io_oeb[14] |mprj_io_oeb[14]
|
|
mprj_io_oeb[23] |mprj_io_oeb[23]
|
|
mprj_io_oeb[13] |mprj_io_oeb[13]
|
|
mprj_io_oeb[22] |mprj_io_oeb[22]
|
|
mprj_io_oeb[7] |mprj_io_oeb[7]
|
|
mprj_io_out[15] |mprj_io_out[15]
|
|
mprj_io_out[23] |mprj_io_out[23]
|
|
mprj_io_out[22] |mprj_io_out[22]
|
|
mprj_io_oeb[21] |mprj_io_oeb[21]
|
|
mprj_io_out[35] |mprj_io_out[35]
|
|
mprj_io_out[34] |mprj_io_out[34]
|
|
mprj_io_out[9] |mprj_io_out[9]
|
|
mprj_io_out[33] |mprj_io_out[33]
|
|
mprj_io_out[13] |mprj_io_out[13]
|
|
mprj_io_out[12] |mprj_io_out[12]
|
|
mprj_io_out[31] |mprj_io_out[31]
|
|
mprj_io_out[21] |mprj_io_out[21]
|
|
mprj_io_out[11] |mprj_io_out[11]
|
|
mprj_io_out[6] |mprj_io_out[6]
|
|
mprj_io_out[20] |mprj_io_out[20]
|
|
mprj_io_out[5] |mprj_io_out[5]
|
|
mprj_io_oeb[36] |mprj_io_oeb[36]
|
|
mprj_io_oeb[35] |mprj_io_oeb[35]
|
|
mprj_io_out[19] |mprj_io_out[19]
|
|
mprj_io_out[28] |mprj_io_out[28]
|
|
mprj_io_out[17] |mprj_io_out[17]
|
|
mprj_io_out[36] |mprj_io_out[36]
|
|
mprj_io_analog_en[24] |mprj_io_analog_en[24]
|
|
mprj_io_analog_en[23] |mprj_io_analog_en[23]
|
|
mprj_io_slow_sel[18] |mprj_io_slow_sel[18]
|
|
mprj_io_slow_sel[16] |mprj_io_slow_sel[16]
|
|
mprj_io_holdover[13] |mprj_io_holdover[13]
|
|
mprj_io_slow_sel[24] |mprj_io_slow_sel[24]
|
|
mprj_io_slow_sel[23] |mprj_io_slow_sel[23]
|
|
mprj_io_inp_dis[16] |mprj_io_inp_dis[16]
|
|
mprj_io_analog_pol[18] |mprj_io_analog_pol[18]
|
|
mprj_io_analog_sel[18] |mprj_io_analog_sel[18]
|
|
mprj_io_analog_sel[37] |mprj_io_analog_sel[37]
|
|
mprj_io_inp_dis[14] |mprj_io_inp_dis[14]
|
|
mprj_io_ib_mode_sel[18] |mprj_io_ib_mode_sel[18]
|
|
mprj_io_ib_mode_sel[37] |mprj_io_ib_mode_sel[37]
|
|
mprj_io_holdover[7] |mprj_io_holdover[7]
|
|
mprj_io_vtrip_sel[18] |mprj_io_vtrip_sel[18]
|
|
mprj_io_holdover[17] |mprj_io_holdover[17]
|
|
mprj_io_vtrip_sel[17] |mprj_io_vtrip_sel[17]
|
|
mprj_io_analog_pol[16] |mprj_io_analog_pol[16]
|
|
mprj_io_vtrip_sel[16] |mprj_io_vtrip_sel[16]
|
|
mprj_io_inp_dis[18] |mprj_io_inp_dis[18]
|
|
mprj_io_holdover[16] |mprj_io_holdover[16]
|
|
mprj_io_ib_mode_sel[17] |mprj_io_ib_mode_sel[17]
|
|
mprj_io_inp_dis[17] |mprj_io_inp_dis[17]
|
|
mprj_io_analog_en[0] |mprj_io_analog_en[0]
|
|
mprj_io_holdover[24] |mprj_io_holdover[24]
|
|
mprj_io_analog_en[18] |mprj_io_analog_en[18]
|
|
mprj_io_analog_en[16] |mprj_io_analog_en[16]
|
|
mprj_io_analog_sel[16] |mprj_io_analog_sel[16]
|
|
mprj_io_ib_mode_sel[16] |mprj_io_ib_mode_sel[16]
|
|
mprj_io_vtrip_sel[14] |mprj_io_vtrip_sel[14]
|
|
mprj_io_analog_pol[24] |mprj_io_analog_pol[24]
|
|
mprj_io_vtrip_sel[37] |mprj_io_vtrip_sel[37]
|
|
mprj_io_vtrip_sel[24] |mprj_io_vtrip_sel[24]
|
|
mprj_io_inp_dis[37] |mprj_io_inp_dis[37]
|
|
mprj_io_vtrip_sel[8] |mprj_io_vtrip_sel[8]
|
|
mprj_io_oeb[29] |mprj_io_oeb[29]
|
|
mprj_io_oeb[28] |mprj_io_oeb[28]
|
|
mprj_io_oeb[27] |mprj_io_oeb[27]
|
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mprj_io_oeb[25] |mprj_io_oeb[25]
|
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mprj_io_oeb[9] |mprj_io_oeb[9]
|
|
mprj_io_oeb[8] |mprj_io_oeb[8]
|
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mprj_io_oeb[12] |mprj_io_oeb[12]
|
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mprj_io_oeb[31] |mprj_io_oeb[31]
|
|
mprj_io_oeb[11] |mprj_io_oeb[11]
|
|
mprj_io_oeb[30] |mprj_io_oeb[30]
|
|
mprj_io_oeb[10] |mprj_io_oeb[10]
|
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mprj_io_out[25] |mprj_io_out[25]
|
|
mprj_io_out[29] |mprj_io_out[29]
|
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mprj_io_out[27] |mprj_io_out[27]
|
|
mprj_io_out[26] |mprj_io_out[26]
|
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mprj_io_slow_sel[30] |mprj_io_slow_sel[30]
|
|
mprj_io_analog_sel[14] |mprj_io_analog_sel[14]
|
|
mprj_io_holdover[30] |mprj_io_holdover[30]
|
|
mprj_io_analog_pol[37] |mprj_io_analog_pol[37]
|
|
mprj_io_holdover[28] |mprj_io_holdover[28]
|
|
mprj_io_holdover[37] |mprj_io_holdover[37]
|
|
mprj_io_slow_sel[37] |mprj_io_slow_sel[37]
|
|
mprj_io_vtrip_sel[7] |mprj_io_vtrip_sel[7]
|
|
mprj_io_vtrip_sel[31] |mprj_io_vtrip_sel[31]
|
|
mprj_io_analog_pol[7] |mprj_io_analog_pol[7]
|
|
mprj_io_slow_sel[34] |mprj_io_slow_sel[34]
|
|
mprj_io_slow_sel[33] |mprj_io_slow_sel[33]
|
|
mprj_io_analog_sel[24] |mprj_io_analog_sel[24]
|
|
mprj_io_vtrip_sel[28] |mprj_io_vtrip_sel[28]
|
|
mprj_io_analog_sel[33] |mprj_io_analog_sel[33]
|
|
mprj_io_vtrip_sel[26] |mprj_io_vtrip_sel[26]
|
|
mprj_io_ib_mode_sel[33] |mprj_io_ib_mode_sel[33]
|
|
mprj_io_vtrip_sel[33] |mprj_io_vtrip_sel[33]
|
|
mprj_io_analog_en[33] |mprj_io_analog_en[33]
|
|
mprj_io_slow_sel[2] |mprj_io_slow_sel[2]
|
|
mprj_io_analog_en[8] |mprj_io_analog_en[8]
|
|
mprj_io_analog_en[12] |mprj_io_analog_en[12]
|
|
mprj_io_slow_sel[29] |mprj_io_slow_sel[29]
|
|
mprj_io_holdover[15] |mprj_io_holdover[15]
|
|
mprj_io_slow_sel[17] |mprj_io_slow_sel[17]
|
|
mprj_io_analog_en[5] |mprj_io_analog_en[5]
|
|
mprj_io_analog_en[2] |mprj_io_analog_en[2]
|
|
mprj_io_analog_en[4] |mprj_io_analog_en[4]
|
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mprj_io_analog_pol[30] |mprj_io_analog_pol[30]
|
|
mprj_io_slow_sel[26] |mprj_io_slow_sel[26]
|
|
mprj_io_slow_sel[13] |mprj_io_slow_sel[13]
|
|
mprj_io_analog_pol[3] |mprj_io_analog_pol[3]
|
|
mprj_io_analog_pol[28] |mprj_io_analog_pol[28]
|
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mprj_io_holdover[2] |mprj_io_holdover[2]
|
|
mprj_io_analog_sel[32] |mprj_io_analog_sel[32]
|
|
mprj_io_analog_pol[17] |mprj_io_analog_pol[17]
|
|
mprj_io_holdover[4] |mprj_io_holdover[4]
|
|
mprj_io_holdover[29] |mprj_io_holdover[29]
|
|
mprj_io_ib_mode_sel[13] |mprj_io_ib_mode_sel[13]
|
|
mprj_io_holdover[3] |mprj_io_holdover[3]
|
|
mprj_io_analog_en[34] |mprj_io_analog_en[34]
|
|
mprj_io_slow_sel[5] |mprj_io_slow_sel[5]
|
|
mprj_io_analog_en[6] |mprj_io_analog_en[6]
|
|
mprj_io_analog_sel[6] |mprj_io_analog_sel[6]
|
|
mprj_io_analog_sel[30] |mprj_io_analog_sel[30]
|
|
mprj_io_analog_sel[10] |mprj_io_analog_sel[10]
|
|
mprj_io_analog_sel[11] |mprj_io_analog_sel[11]
|
|
mprj_io_holdover[27] |mprj_io_holdover[27]
|
|
mprj_io_ib_mode_sel[7] |mprj_io_ib_mode_sel[7]
|
|
mprj_io_ib_mode_sel[11] |mprj_io_ib_mode_sel[11]
|
|
mprj_io_holdover[26] |mprj_io_holdover[26]
|
|
mprj_io_vtrip_sel[13] |mprj_io_vtrip_sel[13]
|
|
mprj_io_analog_pol[9] |mprj_io_analog_pol[9]
|
|
mprj_io_analog_pol[33] |mprj_io_analog_pol[33]
|
|
mprj_io_ib_mode_sel[30] |mprj_io_ib_mode_sel[30]
|
|
mprj_io_holdover[25] |mprj_io_holdover[25]
|
|
mprj_io_analog_pol[32] |mprj_io_analog_pol[32]
|
|
mprj_io_inp_dis[15] |mprj_io_inp_dis[15]
|
|
mprj_io_ib_mode_sel[1] |mprj_io_ib_mode_sel[1]
|
|
mprj_io_holdover[34] |mprj_io_holdover[34]
|
|
mprj_io_vtrip_sel[11] |mprj_io_vtrip_sel[11]
|
|
mprj_io_analog_en[31] |mprj_io_analog_en[31]
|
|
mprj_io_analog_pol[31] |mprj_io_analog_pol[31]
|
|
mprj_io_analog_sel[31] |mprj_io_analog_sel[31]
|
|
mprj_io_ib_mode_sel[31] |mprj_io_ib_mode_sel[31]
|
|
mprj_io_inp_dis[34] |mprj_io_inp_dis[34]
|
|
mprj_io_holdover[9] |mprj_io_holdover[9]
|
|
mprj_io_holdover[33] |mprj_io_holdover[33]
|
|
mprj_io_analog_en[14] |mprj_io_analog_en[14]
|
|
mprj_io_analog_pol[34] |mprj_io_analog_pol[34]
|
|
mprj_io_analog_sel[7] |mprj_io_analog_sel[7]
|
|
mprj_io_vtrip_sel[12] |mprj_io_vtrip_sel[12]
|
|
mprj_io_vtrip_sel[6] |mprj_io_vtrip_sel[6]
|
|
mprj_io_analog_pol[6] |mprj_io_analog_pol[6]
|
|
mprj_io_inp_dis[9] |mprj_io_inp_dis[9]
|
|
mprj_io_inp_dis[33] |mprj_io_inp_dis[33]
|
|
mprj_io_vtrip_sel[32] |mprj_io_vtrip_sel[32]
|
|
mprj_io_analog_sel[17] |mprj_io_analog_sel[17]
|
|
mprj_io_inp_dis[13] |mprj_io_inp_dis[13]
|
|
mprj_io_holdover[8] |mprj_io_holdover[8]
|
|
mprj_io_vtrip_sel[2] |mprj_io_vtrip_sel[2]
|
|
mprj_io_vtrip_sel[0] |mprj_io_vtrip_sel[0]
|
|
mprj_io_inp_dis[8] |mprj_io_inp_dis[8]
|
|
mprj_io_inp_dis[12] |mprj_io_inp_dis[12]
|
|
mprj_io_holdover[31] |mprj_io_holdover[31]
|
|
mprj_io_vtrip_sel[29] |mprj_io_vtrip_sel[29]
|
|
mprj_io_analog_en[9] |mprj_io_analog_en[9]
|
|
mprj_io_slow_sel[9] |mprj_io_slow_sel[9]
|
|
mprj_io_ib_mode_sel[26] |mprj_io_ib_mode_sel[26]
|
|
mprj_io_vtrip_sel[3] |mprj_io_vtrip_sel[3]
|
|
mprj_io_slow_sel[8] |mprj_io_slow_sel[8]
|
|
mprj_io_slow_sel[32] |mprj_io_slow_sel[32]
|
|
mprj_io_analog_sel[9] |mprj_io_analog_sel[9]
|
|
mprj_io_holdover[6] |mprj_io_holdover[6]
|
|
mprj_io_ib_mode_sel[6] |mprj_io_ib_mode_sel[6]
|
|
mprj_io_inp_dis[6] |mprj_io_inp_dis[6]
|
|
mprj_io_inp_dis[30] |mprj_io_inp_dis[30]
|
|
mprj_io_vtrip_sel[27] |mprj_io_vtrip_sel[27]
|
|
mprj_io_slow_sel[7] |mprj_io_slow_sel[7]
|
|
mprj_io_slow_sel[31] |mprj_io_slow_sel[31]
|
|
mprj_io_analog_sel[8] |mprj_io_analog_sel[8]
|
|
mprj_io_holdover[5] |mprj_io_holdover[5]
|
|
mprj_io_ib_mode_sel[5] |mprj_io_ib_mode_sel[5]
|
|
mprj_io_inp_dis[5] |mprj_io_inp_dis[5]
|
|
mprj_io_ib_mode_sel[2] |mprj_io_ib_mode_sel[2]
|
|
mprj_io_inp_dis[2] |mprj_io_inp_dis[2]
|
|
mprj_io_analog_pol[5] |mprj_io_analog_pol[5]
|
|
mprj_io_analog_sel[5] |mprj_io_analog_sel[5]
|
|
mprj_io_ib_mode_sel[34] |mprj_io_ib_mode_sel[34]
|
|
mprj_io_ib_mode_sel[24] |mprj_io_ib_mode_sel[24]
|
|
mprj_io_inp_dis[31] |mprj_io_inp_dis[31]
|
|
mprj_io_inp_dis[11] |mprj_io_inp_dis[11]
|
|
mprj_io_slow_sel[6] |mprj_io_slow_sel[6]
|
|
mprj_io_ib_mode_sel[4] |mprj_io_ib_mode_sel[4]
|
|
mprj_io_inp_dis[4] |mprj_io_inp_dis[4]
|
|
mprj_io_analog_pol[29] |mprj_io_analog_pol[29]
|
|
mprj_io_analog_sel[29] |mprj_io_analog_sel[29]
|
|
mprj_io_ib_mode_sel[29] |mprj_io_ib_mode_sel[29]
|
|
mprj_io_inp_dis[29] |mprj_io_inp_dis[29]
|
|
mprj_io_ib_mode_sel[9] |mprj_io_ib_mode_sel[9]
|
|
mprj_io_vtrip_sel[35] |mprj_io_vtrip_sel[35]
|
|
mprj_io_vtrip_sel[25] |mprj_io_vtrip_sel[25]
|
|
mprj_io_ib_mode_sel[3] |mprj_io_ib_mode_sel[3]
|
|
mprj_io_inp_dis[3] |mprj_io_inp_dis[3]
|
|
mprj_io_inp_dis[28] |mprj_io_inp_dis[28]
|
|
mprj_io_ib_mode_sel[8] |mprj_io_ib_mode_sel[8]
|
|
mprj_io_analog_pol[14] |mprj_io_analog_pol[14]
|
|
mprj_io_vtrip_sel[34] |mprj_io_vtrip_sel[34]
|
|
mprj_io_analog_sel[35] |mprj_io_analog_sel[35]
|
|
mprj_io_inp_dis[27] |mprj_io_inp_dis[27]
|
|
mprj_io_vtrip_sel[9] |mprj_io_vtrip_sel[9]
|
|
mprj_io_ib_mode_sel[36] |mprj_io_ib_mode_sel[36]
|
|
mprj_io_inp_dis[36] |mprj_io_inp_dis[36]
|
|
mprj_io_analog_en[10] |mprj_io_analog_en[10]
|
|
mprj_io_analog_en[11] |mprj_io_analog_en[11]
|
|
mprj_io_analog_en[29] |mprj_io_analog_en[29]
|
|
mprj_io_analog_en[3] |mprj_io_analog_en[3]
|
|
mprj_io_analog_sel[3] |mprj_io_analog_sel[3]
|
|
mprj_io_analog_en[13] |mprj_io_analog_en[13]
|
|
mprj_io_analog_en[28] |mprj_io_analog_en[28]
|
|
mprj_io_analog_pol[13] |mprj_io_analog_pol[13]
|
|
mprj_io_analog_sel[13] |mprj_io_analog_sel[13]
|
|
mprj_io_analog_sel[28] |mprj_io_analog_sel[28]
|
|
mprj_io_ib_mode_sel[28] |mprj_io_ib_mode_sel[28]
|
|
mprj_io_holdover[12] |mprj_io_holdover[12]
|
|
mprj_io_analog_pol[12] |mprj_io_analog_pol[12]
|
|
mprj_io_analog_pol[15] |mprj_io_analog_pol[15]
|
|
mprj_io_analog_en[37] |mprj_io_analog_en[37]
|
|
mprj_io_analog_pol[36] |mprj_io_analog_pol[36]
|
|
mprj_io_analog_sel[36] |mprj_io_analog_sel[36]
|
|
mprj_io_ib_mode_sel[35] |mprj_io_ib_mode_sel[35]
|
|
mprj_io_inp_dis[35] |mprj_io_inp_dis[35]
|
|
mprj_io_slow_sel[36] |mprj_io_slow_sel[36]
|
|
mprj_io_vtrip_sel[36] |mprj_io_vtrip_sel[36]
|
|
mprj_io_analog_en[27] |mprj_io_analog_en[27]
|
|
mprj_io_analog_pol[27] |mprj_io_analog_pol[27]
|
|
mprj_io_analog_pol[35] |mprj_io_analog_pol[35]
|
|
mprj_io_analog_sel[27] |mprj_io_analog_sel[27]
|
|
mprj_io_ib_mode_sel[27] |mprj_io_ib_mode_sel[27]
|
|
mprj_io_slow_sel[27] |mprj_io_slow_sel[27]
|
|
mprj_io_slow_sel[35] |mprj_io_slow_sel[35]
|
|
mprj_io_analog_en[17] |mprj_io_analog_en[17]
|
|
mprj_io_analog_en[1] |mprj_io_analog_en[1]
|
|
mprj_io_analog_pol[1] |mprj_io_analog_pol[1]
|
|
mprj_io_analog_pol[2] |mprj_io_analog_pol[2]
|
|
mprj_io_analog_pol[4] |mprj_io_analog_pol[4]
|
|
mprj_io_analog_sel[1] |mprj_io_analog_sel[1]
|
|
mprj_io_analog_sel[2] |mprj_io_analog_sel[2]
|
|
mprj_io_analog_sel[4] |mprj_io_analog_sel[4]
|
|
mprj_io_inp_dis[1] |mprj_io_inp_dis[1]
|
|
mprj_io_slow_sel[1] |mprj_io_slow_sel[1]
|
|
mprj_io_slow_sel[3] |mprj_io_slow_sel[3]
|
|
mprj_io_slow_sel[4] |mprj_io_slow_sel[4]
|
|
mprj_io_vtrip_sel[4] |mprj_io_vtrip_sel[4]
|
|
mprj_io_holdover[11] |mprj_io_holdover[11]
|
|
mprj_io_inp_dis[10] |mprj_io_inp_dis[10]
|
|
mprj_io_analog_en[36] |mprj_io_analog_en[36]
|
|
mprj_io_holdover[35] |mprj_io_holdover[35]
|
|
mprj_io_analog_en[26] |mprj_io_analog_en[26]
|
|
mprj_io_analog_en[30] |mprj_io_analog_en[30]
|
|
mprj_io_analog_pol[0] |mprj_io_analog_pol[0]
|
|
mprj_io_analog_pol[26] |mprj_io_analog_pol[26]
|
|
mprj_io_analog_pol[8] |mprj_io_analog_pol[8]
|
|
mprj_io_analog_sel[0] |mprj_io_analog_sel[0]
|
|
mprj_io_analog_sel[26] |mprj_io_analog_sel[26]
|
|
mprj_io_ib_mode_sel[0] |mprj_io_ib_mode_sel[0]
|
|
mprj_io_inp_dis[0] |mprj_io_inp_dis[0]
|
|
mprj_io_slow_sel[0] |mprj_io_slow_sel[0]
|
|
mprj_io_holdover[10] |mprj_io_holdover[10]
|
|
mprj_io_inp_dis[7] |mprj_io_inp_dis[7]
|
|
mprj_io_analog_en[35] |mprj_io_analog_en[35]
|
|
mprj_io_holdover[36] |mprj_io_holdover[36]
|
|
mprj_io_analog_en[25] |mprj_io_analog_en[25]
|
|
mprj_io_analog_en[32] |mprj_io_analog_en[32]
|
|
mprj_io_analog_pol[25] |mprj_io_analog_pol[25]
|
|
mprj_io_analog_sel[25] |mprj_io_analog_sel[25]
|
|
mprj_io_holdover[32] |mprj_io_holdover[32]
|
|
mprj_io_ib_mode_sel[25] |mprj_io_ib_mode_sel[25]
|
|
mprj_io_ib_mode_sel[32] |mprj_io_ib_mode_sel[32]
|
|
mprj_io_inp_dis[25] |mprj_io_inp_dis[25]
|
|
mprj_io_inp_dis[32] |mprj_io_inp_dis[32]
|
|
mprj_io_slow_sel[25] |mprj_io_slow_sel[25]
|
|
mprj_io_analog_en[15] |mprj_io_analog_en[15]
|
|
mprj_io_analog_sel[12] |mprj_io_analog_sel[12]
|
|
mprj_io_analog_sel[15] |mprj_io_analog_sel[15]
|
|
mprj_io_ib_mode_sel[15] |mprj_io_ib_mode_sel[15]
|
|
mprj_io_holdover[1] |mprj_io_holdover[1]
|
|
mprj_io_vtrip_sel[1] |mprj_io_vtrip_sel[1]
|
|
mprj_io_holdover[0] |mprj_io_holdover[0]
|
|
mprj_io_analog_en[7] |mprj_io_analog_en[7]
|
|
mprj_io_analog_pol[10] |mprj_io_analog_pol[10]
|
|
mprj_io_analog_pol[11] |mprj_io_analog_pol[11]
|
|
mprj_io_analog_sel[34] |mprj_io_analog_sel[34]
|
|
mprj_io_ib_mode_sel[10] |mprj_io_ib_mode_sel[10]
|
|
mprj_io_ib_mode_sel[12] |mprj_io_ib_mode_sel[12]
|
|
mprj_io_ib_mode_sel[14] |mprj_io_ib_mode_sel[14]
|
|
mprj_io_slow_sel[11] |mprj_io_slow_sel[11]
|
|
mprj_io_slow_sel[12] |mprj_io_slow_sel[12]
|
|
mprj_io_slow_sel[15] |mprj_io_slow_sel[15]
|
|
mprj_io_vtrip_sel[15] |mprj_io_vtrip_sel[15]
|
|
mprj_io_vtrip_sel[5] |mprj_io_vtrip_sel[5]
|
|
flash_io1_oeb |flash_io1_oeb
|
|
flash_io1_ieb |flash_io1_ieb
|
|
flash_io1_do |flash_io1_do
|
|
mprj_io_dm[97] |mprj_io_dm[97]
|
|
mprj_io_dm[102] |mprj_io_dm[102]
|
|
mprj_io_dm[19] |mprj_io_dm[19]
|
|
mprj_io_dm[100] |mprj_io_dm[100]
|
|
mprj_io_dm[112] |mprj_io_dm[112]
|
|
mprj_io_dm[106] |mprj_io_dm[106]
|
|
mprj_io_dm[109] |mprj_io_dm[109]
|
|
mprj_io_dm[10] |mprj_io_dm[10]
|
|
mprj_io_dm[1] |mprj_io_dm[1]
|
|
mprj_io_dm[4] |mprj_io_dm[4]
|
|
mprj_io_dm[7] |mprj_io_dm[7]
|
|
mprj_io_dm[107] |mprj_io_dm[107]
|
|
mprj_io_dm[110] |mprj_io_dm[110]
|
|
mprj_io_dm[11] |mprj_io_dm[11]
|
|
mprj_io_dm[8] |mprj_io_dm[8]
|
|
mprj_io_dm[13] |mprj_io_dm[13]
|
|
mprj_io_dm[16] |mprj_io_dm[16]
|
|
mprj_io_dm[101] |mprj_io_dm[101]
|
|
mprj_io_dm[113] |mprj_io_dm[113]
|
|
mprj_io_dm[2] |mprj_io_dm[2]
|
|
mprj_io_dm[5] |mprj_io_dm[5]
|
|
flash_io0_oeb |flash_io0_oeb
|
|
mprj_io_dm[47] |mprj_io_dm[47]
|
|
flash_io0_ieb |flash_io0_ieb
|
|
mprj_io_dm[48] |mprj_io_dm[48]
|
|
mprj_io_dm[66] |mprj_io_dm[66]
|
|
mprj_io_dm[46] |mprj_io_dm[46]
|
|
flash_io0_do |flash_io0_do
|
|
gpio_out_core |gpio_out_core
|
|
flash_csb_frame |flash_csb_frame
|
|
por_l |por_l
|
|
mprj_io_dm[63] |mprj_io_dm[63]
|
|
gpio_mode1_core |gpio_mode1_core
|
|
mprj_io_dm[27] |mprj_io_dm[27]
|
|
mprj_io_dm[33] |mprj_io_dm[33]
|
|
mprj_io_dm[36] |mprj_io_dm[36]
|
|
mprj_io_dm[39] |mprj_io_dm[39]
|
|
mprj_io_dm[42] |mprj_io_dm[42]
|
|
gpio_mode0_core |gpio_mode0_core
|
|
flash_clk_frame |flash_clk_frame
|
|
flash_clk_oeb |flash_clk_oeb
|
|
flash_csb_oeb |flash_csb_oeb
|
|
gpio_inenb_core |gpio_inenb_core
|
|
mprj_io_dm[54] |mprj_io_dm[54]
|
|
mprj_io_dm[81] |mprj_io_dm[81]
|
|
mprj_io_dm[84] |mprj_io_dm[84]
|
|
mprj_io_dm[87] |mprj_io_dm[87]
|
|
mprj_io_dm[90] |mprj_io_dm[90]
|
|
mprj_io_dm[93] |mprj_io_dm[93]
|
|
mprj_io_dm[72] |mprj_io_dm[72]
|
|
mprj_io_inp_dis[24] |mprj_io_inp_dis[24]
|
|
mprj_io_oeb[19] |mprj_io_oeb[19]
|
|
mprj_io_oeb[33] |mprj_io_oeb[33]
|
|
mprj_io_out[16] |mprj_io_out[16]
|
|
mprj_io_out[8] |mprj_io_out[8]
|
|
mprj_io_out[32] |mprj_io_out[32]
|
|
mprj_io_out[10] |mprj_io_out[10]
|
|
mprj_io_oeb[24] |mprj_io_oeb[24]
|
|
mprj_io_oeb[20] |mprj_io_oeb[20]
|
|
mprj_io_out[14] |mprj_io_out[14]
|
|
mprj_io_oeb[37] |mprj_io_oeb[37]
|
|
mprj_io_oeb[32] |mprj_io_oeb[32]
|
|
mprj_io_out[37] |mprj_io_out[37]
|
|
mprj_io_oeb[5] |mprj_io_oeb[5]
|
|
mprj_io_oeb[2] |mprj_io_oeb[2]
|
|
mprj_io_oeb[1] |mprj_io_oeb[1]
|
|
mprj_io_oeb[0] |mprj_io_oeb[0]
|
|
mprj_io_out[24] |mprj_io_out[24]
|
|
mprj_io_oeb[4] |mprj_io_oeb[4]
|
|
mprj_io_oeb[3] |mprj_io_oeb[3]
|
|
mprj_io_out[7] |mprj_io_out[7]
|
|
mprj_io_out[2] |mprj_io_out[2]
|
|
mprj_io_out[4] |mprj_io_out[4]
|
|
mprj_io_out[1] |mprj_io_out[1]
|
|
mprj_io_out[0] |mprj_io_out[0]
|
|
mprj_io_out[3] |mprj_io_out[3]
|
|
mprj_io_out[18] |mprj_io_out[18]
|
|
mprj_io_oeb[6] |mprj_io_oeb[6]
|
|
mprj_io_analog_pol[22] |mprj_io_analog_pol[22]
|
|
mprj_io_holdover[23] |mprj_io_holdover[23]
|
|
mprj_io_analog_sel[20] |mprj_io_analog_sel[20]
|
|
mprj_io_ib_mode_sel[19] |mprj_io_ib_mode_sel[19]
|
|
mprj_io_ib_mode_sel[20] |mprj_io_ib_mode_sel[20]
|
|
mprj_io_vtrip_sel[19] |mprj_io_vtrip_sel[19]
|
|
mprj_io_vtrip_sel[20] |mprj_io_vtrip_sel[20]
|
|
mprj_io_analog_en[19] |mprj_io_analog_en[19]
|
|
mprj_io_analog_pol[19] |mprj_io_analog_pol[19]
|
|
mprj_io_analog_sel[19] |mprj_io_analog_sel[19]
|
|
mprj_io_holdover[19] |mprj_io_holdover[19]
|
|
mprj_io_holdover[22] |mprj_io_holdover[22]
|
|
mprj_io_ib_mode_sel[22] |mprj_io_ib_mode_sel[22]
|
|
mprj_io_inp_dis[19] |mprj_io_inp_dis[19]
|
|
mprj_io_inp_dis[22] |mprj_io_inp_dis[22]
|
|
mprj_io_inp_dis[23] |mprj_io_inp_dis[23]
|
|
mprj_io_vtrip_sel[21] |mprj_io_vtrip_sel[21]
|
|
mprj_io_vtrip_sel[22] |mprj_io_vtrip_sel[22]
|
|
mprj_io_vtrip_sel[23] |mprj_io_vtrip_sel[23]
|
|
mprj_io_holdover[21] |mprj_io_holdover[21]
|
|
mprj_io_analog_en[20] |mprj_io_analog_en[20]
|
|
mprj_io_holdover[20] |mprj_io_holdover[20]
|
|
mprj_io_inp_dis[20] |mprj_io_inp_dis[20]
|
|
mprj_io_slow_sel[20] |mprj_io_slow_sel[20]
|
|
vccd2 |vccd2
|
|
vssd2 |vssd2
|
|
vdda1 |vdda1
|
|
vssa1 |vssa1
|
|
vdda2 |vdda2
|
|
vssa2 |vssa2
|
|
mprj_analog_io[28] |mprj_analog_io[28]
|
|
mprj_analog_io[27] |mprj_analog_io[27]
|
|
mprj_analog_io[26] |mprj_analog_io[26]
|
|
mprj_analog_io[25] |mprj_analog_io[25]
|
|
mprj_analog_io[24] |mprj_analog_io[24]
|
|
mprj_analog_io[23] |mprj_analog_io[23]
|
|
mprj_analog_io[22] |mprj_analog_io[22]
|
|
mprj_analog_io[21] |mprj_analog_io[21]
|
|
mprj_analog_io[20] |mprj_analog_io[20]
|
|
mprj_analog_io[19] |mprj_analog_io[19]
|
|
mprj_analog_io[18] |mprj_analog_io[18]
|
|
mprj_analog_io[17] |mprj_analog_io[17]
|
|
mprj_analog_io[16] |mprj_analog_io[16]
|
|
mprj_analog_io[15] |mprj_analog_io[15]
|
|
mprj_analog_io[14] |mprj_analog_io[14]
|
|
mprj_analog_io[13] |mprj_analog_io[13]
|
|
mprj_analog_io[12] |mprj_analog_io[12]
|
|
mprj_analog_io[11] |mprj_analog_io[11]
|
|
mprj_analog_io[10] |mprj_analog_io[10]
|
|
mprj_analog_io[9] |mprj_analog_io[9]
|
|
mprj_analog_io[8] |mprj_analog_io[8]
|
|
mprj_analog_io[7] |mprj_analog_io[7]
|
|
mprj_analog_io[6] |mprj_analog_io[6]
|
|
mprj_analog_io[5] |mprj_analog_io[5]
|
|
mprj_analog_io[4] |mprj_analog_io[4]
|
|
mprj_analog_io[3] |mprj_analog_io[3]
|
|
mprj_analog_io[2] |mprj_analog_io[2]
|
|
mprj_analog_io[1] |mprj_analog_io[1]
|
|
mprj_analog_io[0] |mprj_analog_io[0]
|
|
vddio |vddio
|
|
vssio |vssio
|
|
rstb_h |rstb_h
|
|
flash_io1_di |flash_io1_di
|
|
clock_core |clock_core
|
|
mprj_io_in[16] |mprj_io_in[16]
|
|
mprj_io_in[17] |mprj_io_in[17]
|
|
mprj_io_in[19] |mprj_io_in[19]
|
|
mprj_io_in[20] |mprj_io_in[20]
|
|
mprj_io_in[23] |mprj_io_in[23]
|
|
mprj_io_in[13] |mprj_io_in[13]
|
|
mprj_io_in[18] |mprj_io_in[18]
|
|
mprj_io_in[27] |mprj_io_in[27]
|
|
mprj_io_in[26] |mprj_io_in[26]
|
|
mprj_io_in[30] |mprj_io_in[30]
|
|
mprj_io_in[24] |mprj_io_in[24]
|
|
mprj_io_in[34] |mprj_io_in[34]
|
|
mprj_io_in[22] |mprj_io_in[22]
|
|
mprj_io_in[1] |mprj_io_in[1]
|
|
mprj_io_in[36] |mprj_io_in[36]
|
|
mprj_io_in[37] |mprj_io_in[37]
|
|
mprj_io_in[2] |mprj_io_in[2]
|
|
mprj_io_in[3] |mprj_io_in[3]
|
|
mprj_io_in[25] |mprj_io_in[25]
|
|
mprj_io_in[33] |mprj_io_in[33]
|
|
mprj_io_in[11] |mprj_io_in[11]
|
|
mprj_io_in[12] |mprj_io_in[12]
|
|
mprj_io_in[32] |mprj_io_in[32]
|
|
mprj_io_in[5] |mprj_io_in[5]
|
|
mprj_io_in[15] |mprj_io_in[15]
|
|
mprj_io_in[0] |mprj_io_in[0]
|
|
mprj_io_in[35] |mprj_io_in[35]
|
|
mprj_io_in[6] |mprj_io_in[6]
|
|
mprj_io_in[7] |mprj_io_in[7]
|
|
mprj_io_in[8] |mprj_io_in[8]
|
|
mprj_io_in[4] |mprj_io_in[4]
|
|
mprj_io_in[21] |mprj_io_in[21]
|
|
mprj_io_in[31] |mprj_io_in[31]
|
|
flash_io0_di |flash_io0_di
|
|
mprj_io_in[14] |mprj_io_in[14]
|
|
mprj_io_in[28] |mprj_io_in[28]
|
|
mprj_io_in[29] |mprj_io_in[29]
|
|
mprj_io_in[9] |mprj_io_in[9]
|
|
gpio_in_core |gpio_in_core
|
|
mprj_io_in[10] |mprj_io_in[10]
|
|
vssd |vssd
|
|
vccd |vccd
|
|
vssd1_uq0 |(no matching pin)
|
|
---------------------------------------------------------------------------------------
|
|
Cell pin lists are equivalent.
|
|
Device classes caravel_core and caravel_core are equivalent.
|
|
|
|
Final result: Circuits match uniquely.
|
|
.
|