mirror of https://github.com/efabless/caravel.git
154 lines
4.1 KiB
Verilog
154 lines
4.1 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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// Spare logic block. This block can be used for metal mask fixes to
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// a design. It is much larger and more comprehensive than the simple
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// "macro_sparecell" in the HD library, and contains flops, taps, muxes,
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// and diodes in addition to the inverters, NOR, NAND, and constant
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// gates provided by macro_sparecell.
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module spare_logic_block (
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`ifdef USE_POWER_PINS
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inout vccd,
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inout vssd,
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`endif
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output [26:0] spare_xz, // Constant 0 outputs (and block inputs)
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output [3:0] spare_xi, // Inverter outputs
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output spare_xib, // Big inverter output
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output [1:0] spare_xna, // NAND outputs
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output [1:0] spare_xno, // NOR outputs
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output [1:0] spare_xmx, // Mux outputs
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output [1:0] spare_xfq, // Flop noninverted output
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output [1:0] spare_xfqn // Flop inverted output
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);
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wire [3:0] spare_logic_nc;
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wire [26:0] spare_logic1;
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wire [26:0] spare_logic0;
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// Rename the logic0 outputs at the block pins.
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assign spare_xz = spare_logic0;
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sky130_fd_sc_hd__conb_1 spare_logic_const [26:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.HI(spare_logic1),
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.LO(spare_logic0)
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);
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sky130_fd_sc_hd__inv_2 spare_logic_inv [3:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(spare_xi),
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.A(spare_logic0[3:0])
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);
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sky130_fd_sc_hd__inv_8 spare_logic_biginv (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(spare_xib),
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.A(spare_logic0[4])
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);
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sky130_fd_sc_hd__nand2_2 spare_logic_nand [1:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(spare_xna),
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.A(spare_logic0[6:5]),
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.B(spare_logic0[8:7])
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);
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sky130_fd_sc_hd__nor2_2 spare_logic_nor [1:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Y(spare_xno),
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.A(spare_logic0[10:9]),
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.B(spare_logic0[12:11])
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);
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sky130_fd_sc_hd__mux2_2 spare_logic_mux [1:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.X(spare_xmx),
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.A0(spare_logic0[14:13]),
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.A1(spare_logic0[16:15]),
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.S(spare_logic0[18:17])
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);
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sky130_fd_sc_hd__dfbbp_1 spare_logic_flop [1:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.Q(spare_xfq),
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.Q_N(spare_xfqn),
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.D(spare_logic0[20:19]),
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.CLK(spare_logic0[22:21]),
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.SET_B(spare_logic0[24:23]),
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.RESET_B(spare_logic0[26:25])
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);
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sky130_fd_sc_hd__tapvpwrvgnd_1 spare_logic_tap [1:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd)
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`endif
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);
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sky130_fd_sc_hd__diode_2 spare_logic_diode [3:0] (
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`ifdef USE_POWER_PINS
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.VPWR(vccd),
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.VGND(vssd),
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.VPB(vccd),
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.VNB(vssd),
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`endif
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.DIODE(spare_logic_nc)
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);
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endmodule
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`default_nettype wire
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