mirror of https://github.com/efabless/caravel.git
272 lines
9.6 KiB
Verilog
272 lines
9.6 KiB
Verilog
// `default_nettype none
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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/*--------------------------------------------------------------*/
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/* caravel_openframe, a project harness for the Google/SkyWater */
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/* sky130 fabrication process and open source PDK */
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/* */
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/* Copyright 2023 Efabless Corporation */
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/* Written by Tim Edwards, March 2023 */
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/* This file is open source hardware released under the */
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/* Apache 2.0 license. See file LICENSE. */
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/* */
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/* The caravel_openframe is a chip top level design conforming */
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/* to the pad locations and assignments used by the Caravel and */
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/* Caravan chips top level definition. However, it does not */
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/* define any embedded processor or other interfaces. */
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/* */
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/* The padframe of caravel_openframe consists of the same 38 */
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/* general-purpose I/O pads as Caravel. The pads formerly */
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/* used by Caravel for dedicated functions of the management */
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/* SoC (flash controller CSB, SCK, IO0 and IO1, gpio, and */
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/* clock) are redefined as additional general-purpose I/O for */
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/* a total of 44 GPIO pads. The resetb pad retains its */
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/* function as an input pin with weak pull-up with high and */
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/* low voltage domain (3.3V and 1.8V) versions of the output */
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/* exported to the chip project core. The user may elect to */
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/* use the reset pin for a purpose other than a master reset. */
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/* */
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/* The padframe implements a simple power-on reset circuit, and */
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/* provides a 32-bit bus in the 1.8V digital domain consisting */
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/* of the (fixed) user project ID. */
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/* */
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/* Each GPIO pad must be configured by the user project. The */
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/* padframe exports constant value "1" and "0" bits in the 1.8V */
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/* domain for each GPIO pad that can be used by the user */
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/* project to loop back to the GPIO to set a static */
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/* configuration on power-up. */
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/* */
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/* Every user project must instantiate a module called */
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/* "openframe_project_wrapper" that connects to all of the */
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/* signals as defined in the module call, below. The layout */
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/* of the user project must correspond to the provided wrapper */
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/* cell layout, describing the position of signal and power */
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/* pins on the perimeter of the wrapper. */
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/* */
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/* Bon voyage! */
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/*--------------------------------------------------------------*/
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/*--------------------------------------------------------------*/
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/* NOTE: This file can be checked for syntax directly using: */
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/* */
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/* iverilog -I ${PDK_ROOT}/${PDK} -DSIM -DFUNCTIONAL \ */
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/* openframe_netlists.v __openframe_project_wrapper.v \ */
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/* -s caravel_openframe */
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/*--------------------------------------------------------------*/
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module caravel_openframe (
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// All top-level I/O are package-facing pins
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inout vddio, // Common 3.3V padframe/ESD power
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inout vddio_2, // Common 3.3V padframe/ESD power
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inout vssio, // Common padframe/ESD ground
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inout vssio_2, // Common padframe/ESD ground
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inout vdda, // Management 3.3V power
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inout vssa, // Common analog ground
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inout vccd, // Management/Common 1.8V power
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inout vssd, // Common digital ground
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inout vdda1, // User area 1 3.3V power
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inout vdda1_2, // User area 1 3.3V power
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inout vdda2, // User area 2 3.3V power
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inout vssa1, // User area 1 analog ground
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inout vssa1_2, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V power
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inout vccd2, // User area 2 1.8V power
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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inout [`OPENFRAME_IO_PADS-1:0] gpio,
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input resetb // Reset input (sense inverted)
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);
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//------------------------------------------------------------
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// This value is uniquely defined for each user project.
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//------------------------------------------------------------
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parameter USER_PROJECT_ID = 32'h00000000;
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// Project Control (pad-facing)
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wire [`OPENFRAME_IO_PADS-1:0] gpio_inp_dis;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_oeb;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_ib_mode_sel;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_vtrip_sel;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_slow_sel;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_holdover;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_analog_en;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_analog_sel;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_analog_pol;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_dm0;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_dm1;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_dm2;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_in;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_in_h;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_out;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_loopback_zero;
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wire [`OPENFRAME_IO_PADS-1:0] gpio_loopback_one;
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wire [`OPENFRAME_IO_PADS-1:0] analog_io;
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wire [`OPENFRAME_IO_PADS-1:0] analog_noesd_io;
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// Power-on-reset signal. The simple POR circuit generates these
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// three signals, uses them to enable the GPIO, and exports the
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// signals to the core.
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wire porb_h;
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wire porb_l;
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wire por_l;
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// Master reset signal. The reset pad generates the sense-inverted
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// reset at 3.3V. The 1.8V signal is derived.
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wire rstb_h;
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wire rstb_l;
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// Mask revision: Output from the padframe, exporting the 32-bit
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// user ID value.
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wire [31:0] mask_rev;
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chip_io_openframe #(
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.USER_PROJECT_ID(USER_PROJECT_ID)
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) padframe (
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// Pad side power connections
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`ifndef TOP_ROUTING
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// Package Pins
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.vddio_pad (vddio), // Common padframe/ESD supply
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.vddio_pad2 (vddio_2),
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.vssio_pad (vssio), // Common padframe/ESD ground
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.vssio_pad2 (vssio_2),
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.vccd_pad (vccd), // Common 1.8V supply
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.vssd_pad (vssd), // Common digital ground
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.vdda_pad (vdda), // Management analog 3.3V supply
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.vssa_pad (vssa), // Management analog ground
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.vdda1_pad (vdda1), // User area 1 3.3V supply
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.vdda1_pad2 (vdda1_2),
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.vdda2_pad (vdda2), // User area 2 3.3V supply
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.vssa1_pad (vssa1), // User area 1 analog ground
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.vssa1_pad2 (vssa1_2),
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.vssa2_pad (vssa2), // User area 2 analog ground
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.vccd1_pad (vccd1), // User area 1 1.8V supply
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.vccd2_pad (vccd2), // User area 2 1.8V supply
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.vssd1_pad (vssd1), // User area 1 digital ground
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.vssd2_pad (vssd2), // User area 2 digital ground
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`endif
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// Pad side signals
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.resetb_pad(resetb),
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.gpio(gpio),
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// Core side power connections
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.vddio (vddio_core),
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.vssio (vssio_core),
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.vdda (vdda_core),
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.vssa (vssa_core),
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.vccd (vccd_core),
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.vssd (vssd_core),
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.vdda1 (vdda1_core),
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.vdda2 (vdda2_core),
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.vssa1 (vssa1_core),
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.vssa2 (vssa2_core),
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.vccd1 (vccd1_core),
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.vccd2 (vccd2_core),
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.vssd1 (vssd1_core),
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.vssd2 (vssd2_core),
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// Core side signals
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.porb_h(porb_h),
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.porb_l(porb_l),
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.por_l(por_l),
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.resetb_h(rstb_h),
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.resetb_l(rstb_l),
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.mask_rev(mask_rev),
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.gpio_in(gpio_in),
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.gpio_in_h(gpio_in_h),
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.gpio_out(gpio_out),
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.gpio_oeb(gpio_oeb),
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.gpio_inp_dis(gpio_inp_dis),
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.gpio_ib_mode_sel(gpio_ib_mode_sel),
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.gpio_vtrip_sel(gpio_vtrip_sel),
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.gpio_slow_sel(gpio_slow_sel),
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.gpio_holdover(gpio_holdover),
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.gpio_analog_en(gpio_analog_en),
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.gpio_analog_sel(gpio_analog_sel),
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.gpio_analog_pol(gpio_analog_pol),
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.gpio_dm0(gpio_dm0),
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.gpio_dm1(gpio_dm1),
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.gpio_dm2(gpio_dm2),
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.gpio_loopback_zero(gpio_loopback_zero),
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.gpio_loopback_one(gpio_loopback_one),
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.analog_io(analog_io),
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.analog_noesd_io(analog_noesd_io)
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);
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/*--------------------------------------------------*/
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/* Wrapper module around the user project */
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/*--------------------------------------------------*/
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openframe_project_wrapper user_project (
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`ifdef USE_POWER_PINS
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.vdda(vdda_core),
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.vssa(vssa_core),
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.vccd(vccd_core),
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.vssd(vssd_core),
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.vdda1(vdda1_core), // User area 1 3.3V power
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.vdda2(vdda2_core), // User area 2 3.3V power
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.vssa1(vssa1_core), // User area 1 analog ground
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.vssa2(vssa2_core), // User area 2 analog ground
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.vccd1(vccd1_core), // User area 1 1.8V power
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.vccd2(vccd2_core), // User area 2 1.8V power
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.vssd1(vssd1_core), // User area 1 digital ground
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.vssd2(vssd2_core), // User area 2 digital ground
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`endif
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.porb_h(porb_h),
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.porb_l(porb_l),
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.por_l(por_l),
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.resetb_h(rstb_h),
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.resetb_l(rstb_l),
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.mask_rev(mask_rev),
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.gpio_in(gpio_in),
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.gpio_in_h(gpio_in_h),
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.gpio_out(gpio_out),
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.gpio_oeb(gpio_oeb),
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.gpio_inp_dis(gpio_inp_dis),
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.gpio_ib_mode_sel(gpio_ib_mode_sel),
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.gpio_vtrip_sel(gpio_vtrip_sel),
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.gpio_slow_sel(gpio_slow_sel),
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.gpio_holdover(gpio_holdover),
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.gpio_analog_en(gpio_analog_en),
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.gpio_analog_sel(gpio_analog_sel),
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.gpio_analog_pol(gpio_analog_pol),
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.gpio_dm0(gpio_dm0),
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.gpio_dm1(gpio_dm1),
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.gpio_dm2(gpio_dm2),
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.gpio_loopback_zero(gpio_loopback_zero),
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.gpio_loopback_one(gpio_loopback_one),
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.analog_io(analog_io),
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.analog_noesd_io(analog_noesd_io)
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);
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/*------------------------------------------*/
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/* End user project instantiation */
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/*------------------------------------------*/
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endmodule
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// `default_nettype wire
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