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__user_analog_project_wrapper.v
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Modified all of the Makefiles to better handle the GL netlist simulations,
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2021-12-03 17:13:53 -05:00 |
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__user_project_wrapper.v
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Modified all of the Makefiles to better handle the GL netlist simulations,
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2021-12-03 17:13:53 -05:00 |
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caravan-signoff.v
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signoff views for caravan
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2022-10-22 07:01:29 -07:00 |
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caravan.v
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changed `caravel_logo`, `caravel_motto`, `copyright_block` to `caravan_logo`, `caravan_motto`, `copyright_block_a` respectively in `verilog/gl/caravan.v` to match the layout
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2023-06-01 13:46:47 -07:00 |
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caravan_core-gl-ecos.txt
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add the analog connections in `caravan_core` GL
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2023-05-24 00:42:28 -07:00 |
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caravan_core-openlane.v
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swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue
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2023-05-30 22:33:33 -07:00 |
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caravan_core.v
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Fixed verilog instance name and ports.
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2024-09-01 08:23:15 -07:00 |
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caravan_signal_routing.v
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update `caravan_signal_routing` to get aligned with `caravan_core`
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2023-05-23 03:19:33 -07:00 |
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caravel.v
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reharden caravel using the modified chip_io.
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2023-02-27 11:19:33 -08:00 |
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caravel_clocking.v
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reharden caravel_clocking.
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2023-02-27 10:26:19 -08:00 |
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caravel_core.v
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Fixed verilog instance name and ports.
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2024-09-01 08:23:15 -07:00 |
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caravel_logo.v
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add missing GLs.
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2023-02-27 11:44:04 -08:00 |
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caravel_motto.v
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add missing GLs.
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2023-02-27 11:44:04 -08:00 |
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caravel_openframe-example.v
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Added pins "vddio" and "vssio" to the openframe and openframe project
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2023-10-18 12:47:56 -04:00 |
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caravel_openframe.v
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Added pins "vddio" and "vssio" to the openframe and openframe project
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2023-10-18 12:47:56 -04:00 |
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chip_io.v
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~ regenerate chip_io netlist to fix missing power pins from constant blocks
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2022-10-12 11:40:05 -07:00 |
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chip_io_alt.v
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Added gl netlists for chip_io_alt and gpio_signal_buffering_alt (#327)
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2022-10-21 12:06:20 -07:00 |
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chip_io_openframe.v
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After updating from the PR that adds the gate level chip_io_openframe.v,
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2023-09-25 20:10:37 -04:00 |
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constant_block.v
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Added constant block openlane files and powered gl and modified housekeeping config.tcl
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2022-10-12 04:12:27 -07:00 |
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copyright_block.v
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add missing GLs.
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2023-02-27 11:44:04 -08:00 |
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empty_macro.v
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Add empty_macro which acts as a placement obstruction.
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2023-02-27 08:14:55 -08:00 |
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empty_macro_1.v
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add `empty_macro_1`
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2023-05-22 06:05:08 -07:00 |
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gpio_defaults_block.v
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updated physical verification reports
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2023-04-26 17:33:44 +02:00 |
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gpio_defaults_block_0403.v
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Modified the GL netlists to match the layout for the GPIO defaults
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2021-11-29 20:17:11 -05:00 |
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gpio_defaults_block_0801.v
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Corrected the pull-up definition and revised the CSB definition to
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2022-10-05 10:02:24 -04:00 |
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gpio_defaults_block_1803.v
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Modified the GL netlists to match the layout for the GPIO defaults
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2021-11-29 20:17:11 -05:00 |
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gpio_logic_high.v
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reharden gpio_logic_high.
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2023-02-27 10:29:46 -08:00 |
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housekeeping.v
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Fixed verilog instance name and ports.
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2024-09-01 08:23:15 -07:00 |
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housekeeping_alt.v
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Fixed verilog instance name and ports.
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2024-09-01 08:23:15 -07:00 |
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manual_power_connections.v
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Added manual_power_connections.
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2023-02-27 08:15:35 -08:00 |
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mgmt_protect.v
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Update Openlane views
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2022-10-27 09:53:45 -07:00 |
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mgmt_protect_hv.v
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Fix mgmt_protect_hv gate-level netlist
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2021-12-07 13:38:30 +02:00 |
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mprj2_logic_high.v
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[DATA] Add views for the mgmt_protect
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2021-11-15 13:21:52 +02:00 |
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mprj_io_buffer.v
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harden mprj_io_buffer.
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2023-02-27 10:33:48 -08:00 |
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mprj_logic_high.v
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[DATA] Add views for the mgmt_protect
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2021-11-15 13:21:52 +02:00 |
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open_source.v
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add missing GLs.
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2023-02-27 11:44:04 -08:00 |
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spare_logic_block.v
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reharden spare_logic_block.
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2023-02-27 10:37:00 -08:00 |
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user_id_programming.v
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[DATA] Add gds/lef/maglef/gl views for the user_id_programming block
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2021-11-15 18:17:32 +02:00 |
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user_id_textblock.v
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add missing GLs.
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2023-02-27 11:44:04 -08:00 |
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xres_buf.v
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[DATA] Add views for xres_buf
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2021-11-15 18:07:02 +02:00 |
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