mirror of https://github.com/efabless/caravel.git
109 lines
3.9 KiB
Bash
Executable File
109 lines
3.9 KiB
Bash
Executable File
#!/bin/bash
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#---------------------------------------------------------------------------
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#
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# Run full LVS on caravel: This does not include verification of underlying
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# library components such as the I/O cells, standard cells, and SRAM, but
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# does include all sub-blocks of caravel.
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#
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#---------------------------------------------------------------------------
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echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
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echo ${PDK:=sky130A} > /dev/null
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# Extract full layout netlist
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cd ../mag
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if [ ! -f caravel.spice ]; then
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magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
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drc off
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crashbackups stop
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load caravel
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# Replace the management core wrapper abstract view with the full view
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cellname filepath mgmt_core_wrapper ../../caravel_mgmt_soc_litex/mag
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flush mgmt_core_wrapper
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select top cell
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expand
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# Replace the SRAM full view with the abstract view.
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cellname filepath sky130_sram_2kbyte_1rw1r_32x512_8 $PDK_ROOT/$PDK/libs.ref/sky130_sram_macros/maglef
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flush sky130_sram_2kbyte_1rw1r_32x512_8
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extract do local
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extract all
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ext2spice lvs
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ext2spice
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EOF
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rm -f *.ext
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# Generate black-box verilog entry for the conb cell. Otherwise, the verilog tends to
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# have only one of the pins listed which will result in an incorrect pin match.
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# Also set the USE_POWER_PINS definition, which is not set anywhere else.
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cat > conb.v << EOF
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\`define USE_POWER_PINS 1
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/* Black-box entry for conb_1 module */
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module sky130_fd_sc_hd__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
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output HI;
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output LO;
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input VPWR;
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input VGND;
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input VPB;
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input VNB;
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endmodule
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/* Black-box entry for conb_1 module */
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module sky130_fd_sc_hvl__conb_1 (HI, LO, VPWR, VGND, VPB, VNB);
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output HI;
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output LO;
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input VPWR;
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input VGND;
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input VPB;
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input VNB;
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endmodule
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EOF
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# Generate script for netgen
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cat > netgen.tcl << EOF
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# Load top level netlists
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puts stdout "Reading netlist caravel.spice"
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set circuit1 [readnet spice caravel.spice]
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puts stdout "Reading gate-level netlist caravel.v"
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set circuit2 [readnet verilog ../verilog/rtl/defines.v]
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# Read additional subcircuits into the netlist of circuit2
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puts stdout "Reading black-box modules"
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readnet verilog conb.v \$circuit2
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puts stdout "Reading all gate-level verilog modules"
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# NOTE: Cannot use __user_project_wrapper.v because it is not
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# equivalent to the layout empty wrapper.
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# readnet verilog ../verilog/gl/__user_project_wrapper.v \$circuit2
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readnet verilog ../verilog/gl/caravel_clocking.v \$circuit2
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readnet verilog ../verilog/gl/chip_io.v \$circuit2
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readnet verilog ../verilog/gl/digital_pll.v \$circuit2
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readnet verilog ../verilog/gl/gpio_control_block.v \$circuit2
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readnet verilog ../verilog/gl/gpio_defaults_block.v \$circuit2
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readnet verilog ../verilog/gl/gpio_defaults_block_1803.v \$circuit2
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readnet verilog ../verilog/gl/gpio_defaults_block_0403.v \$circuit2
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readnet verilog ../verilog/gl/gpio_logic_high.v \$circuit2
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readnet verilog ../verilog/gl/housekeeping.v \$circuit2
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readnet verilog ../verilog/gl/mgmt_protect_hv.v \$circuit2
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readnet verilog ../verilog/gl/mgmt_protect.v \$circuit2
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readnet verilog ../verilog/gl/mprj2_logic_high.v \$circuit2
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readnet verilog ../verilog/gl/mprj_logic_high.v \$circuit2
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readnet verilog ../verilog/gl/spare_logic_block.v \$circuit2
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readnet verilog ../verilog/gl/user_id_programming.v \$circuit2
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readnet verilog ../verilog/gl/xres_buf.v \$circuit2
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readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/DFFRAM.v \$circuit2
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readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core.v \$circuit2
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readnet verilog ../../caravel_mgmt_soc_litex/verilog/gl/mgmt_core_wrapper.v \$circuit2
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readnet verilog ../verilog/gl/caravel.v \$circuit2
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# Run LVS
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lvs "\$circuit1 caravel" "\$circuit2 caravel" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl caravel_full_comp.out
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EOF
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export NETGEN_COLUMNS=60
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export MAGIC_EXT_USE_GDS=1
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netgen -batch source netgen.tcl
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rm conb.v
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rm netgen.tcl
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mv caravel.spice ../spi/lvs/caravel_lvs_full.spice
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mv caravel_full_comp.out ../signoff/
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exit 0
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