mirror of https://github.com/efabless/caravel.git
155 lines
7.2 KiB
Tcl
155 lines
7.2 KiB
Tcl
### Housekeeping SDC Update
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### Mod Rev 2
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### Date: 7/10/2022
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set ::env(WB_CLK_PERIOD) 25
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set ::env(SCK_CLK_PERIOD) 100
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set ::env(RESET_PORT) "wb_rstn_i"
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set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
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## MASTER CLOCKS
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create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i" -period $::env(WB_CLK_PERIOD)
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create_clock [get_ports {"user_clock"} ] -name "user_clock" -period $::env(WB_CLK_PERIOD)
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create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "sck" -period $::env(SCK_CLK_PERIOD)
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##
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set_propagated_clock [get_clocks {wb_clk_i}]
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set_propagated_clock [get_clocks {user_clock}]
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set_propagated_clock [get_clocks {"sck"}]
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## GENERATED CLOCKS
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# NOTE: change the clock pins whenever the synthesis receipe changes
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set wbbd_sck_pin [get_pins -of_objects wbbd_sck -filter lib_pin_name==Q]
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create_generated_clock -name "wbbd_sck" -source [get_ports {"wb_clk_i"} ] -divide_by 2 $wbbd_sck_pin
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# paths between wb_clk_i and sck shouldn't be timed
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set_clock_groups -logically_exclusive -group wb_clk_i -group sck
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set_propagated_clock [all_clocks]
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## FALSE PATHS
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set_false_path -from [get_ports $::env(RESET_PORT)]
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set_false_path -from [get_ports "porb"]
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## INPUT/OUTPUT DELAYS
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set input_delay_value 5
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set output_delay_value 5
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puts "\[INFO\]: Setting output delay to: $output_delay_value"
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puts "\[INFO\]: Setting input delay to: $input_delay_value"
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## INPUT DELAYS
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set_input_delay $input_delay_value -clock [get_clocks wb_clk_i] [all_inputs]
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set_input_delay 0 -clock [get_clocks wb_clk_i] [get_port "mgmt_gpio_in[4]"]
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# set_input_delay 0 -clock [get_clocks wb_clk_i] [get_port "wb_clk_i"]
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set_input_delay 0 -clock [get_clocks wb_clk_i] [get_port "user_clock"]
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## OUTPUT DELAYS
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# WISHBONE DELAY
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set_output_delay 0 -clock [get_clocks wb_clk_i] [get_ports wb_ack_o]
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set_output_delay -1.5 -clock [get_clocks wb_clk_i] [get_ports wb_dat_o[*]]
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# PLL DELAYS
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_ena]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_dco_ena]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_div[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_sel[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll90_sel[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_trim[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_bypass]
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# SOC DELAYS
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports ser_rx]
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# SPI DELAYS
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spi_sdi]
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# IRQ
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports irq[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports reset]
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# GPIO
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# Specify serial_clock as a generated clock signal
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#set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_clock]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_load]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_resetn]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_data_1]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_data_2]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports mgmt_gpio_out[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports mgmt_gpio_oeb[*]]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pwr_ctrl_out[*]]
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# FLASH
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io0_di]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io1_di]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io2_di]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io3_di]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports debug_in]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_csb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_csb_oeb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_clk]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_clk_oeb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_oeb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_oeb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_ieb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_ieb]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_do]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_do]
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set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_ieb]
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# SRAM
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# set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_clk]
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# set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_csb]
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# set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_addr[*]]
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## OUTPUT LOADS
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set PT_cap_load 0.21
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puts "\[INFO\]: Setting load to: $PT_cap_load"
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set_load $PT_cap_load [all_outputs]
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## TIMING DERATE
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set ::env(SYNTH_TIMING_DERATE) 0.05
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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## CLOCK UNCERTAINITY
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set wb_clk_uncer 0.28
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set sck_clk_uncer 0.28
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puts "\[INFO\]: Setting WB clock uncertainity to: $wb_clk_uncer"
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puts "\[INFO\]: Setting SCK clock uncertainity to: $sck_clk_uncer"
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set_clock_uncertainty $wb_clk_uncer [get_clocks {wb_clk_i}]
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set_clock_uncertainty $wb_clk_uncer [get_clocks {user_clock}]
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set_clock_uncertainty $sck_clk_uncer [get_clocks {sck}]
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set_clock_uncertainty $sck_clk_uncer [get_clocks {wbbd_sck}]
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## CLOCK TRANSITION
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set wb_clk_tran 0.15
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set sck_clk_tran 0.15
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puts "\[INFO\]: Setting clock transition to: $wb_clk_tran"
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puts "\[INFO\]: Setting clock transition to: $sck_clk_tran"
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set_clock_transition $wb_clk_tran [get_clocks {wb_clk_i}]
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set_clock_transition $wb_clk_tran [get_clocks {user_clock}]
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set_clock_transition $sck_clk_tran [get_clocks {sck}]
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## FANOUT
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puts "\[INFO\]: Setting maximum fanout to: $::env(SYNTH_MAX_FANOUT)"
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set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
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## MAX Transition
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set_max_trans 0.70 [current_design]
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set_max_transition 0.4 [get_clocks {wb_clk_i}] -clock_path
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set_max_transition 0.4 [get_clocks {user_clock}] -clock_path
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set_max_transition 0.4 [get_clocks {sck}] -clock_path
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set_max_transition 0.4 [get_ports {pad_flash_clk}] -clock_path
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set_max_transition 0.4 [get_ports {mgmt_gpio_out[15]}] -clock_path
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set_max_transition 0.4 [get_ports {mgmt_gpio_out[9]}] -clock_path
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set_max_transition 0.4 [get_ports {mgmt_gpio_out[14]}] -clock_path
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