mirror of https://github.com/efabless/caravel.git
2772 lines
128 KiB
Modula-2
2772 lines
128 KiB
Modula-2
VERSION 5.7 ;
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NAMESCASESENSITIVE ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "()" ;
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DESIGN openframe_project_wrapper ;
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TECHNOLOGY sky130A ;
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UNITS DISTANCE MICRONS 1000 ;
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DIEAREA ( 0 0 ) ( 3166630 4766630 ) ;
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VIAS 0 ;
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END VIAS
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COMPONENTS 0 ;
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END COMPONENTS
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PINS 917 ;
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- gpio_vtrip_sel[43] + NET gpio_vtrip_sel[43]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2429490 -860 ) N ;
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- gpio_analog_en[15] + NET gpio_analog_en[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2970160 4767490 ) N ;
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- gpio_analog_pol[15] + NET gpio_analog_pol[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2963720 4767490 ) N ;
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- gpio_analog_sel[15] + NET gpio_analog_sel[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2948540 4767490 ) N ;
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- gpio_dm0[15] + NET gpio_dm0[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2966940 4767490 ) N ;
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- gpio_dm1[15] + NET gpio_dm1[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2976140 4767490 ) N ;
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- gpio_dm2[15] + NET gpio_dm2[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2945320 4767490 ) N ;
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- gpio_holdover[15] + NET gpio_holdover[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2942100 4767490 ) N ;
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- gpio_ib_mode_sel[15] + NET gpio_ib_mode_sel[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2926920 4767490 ) N ;
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- gpio_inp_dis[15] + NET gpio_inp_dis[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2960960 4767490 ) N ;
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- gpio_oeb[15] + NET gpio_oeb[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2923700 4767490 ) N ;
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- gpio_out[15] + NET gpio_out[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2939340 4767490 ) N ;
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- gpio_slow_sel[15] + NET gpio_slow_sel[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2985340 4767490 ) N ;
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- gpio_vtrip_sel[15] + NET gpio_vtrip_sel[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2930140 4767490 ) N ;
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- gpio_in[15] + NET gpio_in[15]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2994540 4767490 ) N ;
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- gpio_analog_en[16] + NET gpio_analog_en[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2461160 4767490 ) N ;
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- gpio_analog_pol[16] + NET gpio_analog_pol[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2454720 4767490 ) N ;
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- gpio_analog_sel[16] + NET gpio_analog_sel[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2439540 4767490 ) N ;
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- gpio_dm0[16] + NET gpio_dm0[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2457940 4767490 ) N ;
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- gpio_dm1[16] + NET gpio_dm1[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2467140 4767490 ) N ;
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- gpio_dm2[16] + NET gpio_dm2[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2436320 4767490 ) N ;
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- gpio_holdover[16] + NET gpio_holdover[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2433100 4767490 ) N ;
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- gpio_ib_mode_sel[16] + NET gpio_ib_mode_sel[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2417920 4767490 ) N ;
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- gpio_inp_dis[16] + NET gpio_inp_dis[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2451960 4767490 ) N ;
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- gpio_oeb[16] + NET gpio_oeb[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2414700 4767490 ) N ;
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- gpio_out[16] + NET gpio_out[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2430340 4767490 ) N ;
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- gpio_slow_sel[16] + NET gpio_slow_sel[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2476340 4767490 ) N ;
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- gpio_vtrip_sel[16] + NET gpio_vtrip_sel[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2421140 4767490 ) N ;
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- gpio_in[16] + NET gpio_in[16]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2485540 4767490 ) N ;
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- gpio_dm1[17] + NET gpio_dm1[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2210140 4767490 ) N ;
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- gpio_dm2[17] + NET gpio_dm2[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2179320 4767490 ) N ;
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- gpio_holdover[17] + NET gpio_holdover[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2176100 4767490 ) N ;
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- gpio_ib_mode_sel[17] + NET gpio_ib_mode_sel[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2160920 4767490 ) N ;
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- gpio_inp_dis[17] + NET gpio_inp_dis[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2194960 4767490 ) N ;
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- gpio_oeb[17] + NET gpio_oeb[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2157700 4767490 ) N ;
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- gpio_out[17] + NET gpio_out[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2173340 4767490 ) N ;
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- gpio_slow_sel[17] + NET gpio_slow_sel[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2219340 4767490 ) N ;
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- gpio_vtrip_sel[17] + NET gpio_vtrip_sel[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2164140 4767490 ) N ;
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- gpio_in[17] + NET gpio_in[17]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2228540 4767490 ) N ;
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- gpio_analog_en[18] + NET gpio_analog_en[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1759160 4767490 ) N ;
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- gpio_analog_pol[18] + NET gpio_analog_pol[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1752720 4767490 ) N ;
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- gpio_analog_sel[18] + NET gpio_analog_sel[18]
|
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1737540 4767490 ) N ;
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- gpio_dm0[18] + NET gpio_dm0[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1755940 4767490 ) N ;
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- gpio_dm1[18] + NET gpio_dm1[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1765140 4767490 ) N ;
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- gpio_dm2[18] + NET gpio_dm2[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1734320 4767490 ) N ;
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- gpio_holdover[18] + NET gpio_holdover[18]
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1731100 4767490 ) N ;
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- gpio_ib_mode_sel[18] + NET gpio_ib_mode_sel[18]
|
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1715920 4767490 ) N ;
|
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- gpio_inp_dis[18] + NET gpio_inp_dis[18]
|
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+ PORT
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1749960 4767490 ) N ;
|
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- gpio_oeb[18] + NET gpio_oeb[18]
|
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+ PORT
|
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1712700 4767490 ) N ;
|
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- gpio_out[18] + NET gpio_out[18]
|
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+ PORT
|
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1728340 4767490 ) N ;
|
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- gpio_slow_sel[18] + NET gpio_slow_sel[18]
|
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+ PORT
|
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1774340 4767490 ) N ;
|
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- gpio_vtrip_sel[18] + NET gpio_vtrip_sel[18]
|
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+ PORT
|
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1719140 4767490 ) N ;
|
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- gpio_in[18] + NET gpio_in[18]
|
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+ PORT
|
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+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1783540 4767490 ) N ;
|
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- gpio_analog_en[17] + NET gpio_analog_en[17]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2204160 4767490 ) N ;
|
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- gpio_analog_pol[17] + NET gpio_analog_pol[17]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2197720 4767490 ) N ;
|
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- gpio_analog_sel[17] + NET gpio_analog_sel[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2182540 4767490 ) N ;
|
|
- gpio_dm0[17] + NET gpio_dm0[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2200940 4767490 ) N ;
|
|
- gpio_slow_sel[19] + NET gpio_slow_sel[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1265340 4767490 ) N ;
|
|
- gpio_vtrip_sel[19] + NET gpio_vtrip_sel[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1210140 4767490 ) N ;
|
|
- gpio_in[19] + NET gpio_in[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1274540 4767490 ) N ;
|
|
- gpio_analog_en[20] + NET gpio_analog_en[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 992160 4767490 ) N ;
|
|
- gpio_analog_pol[20] + NET gpio_analog_pol[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 985720 4767490 ) N ;
|
|
- gpio_analog_sel[20] + NET gpio_analog_sel[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 970540 4767490 ) N ;
|
|
- gpio_dm0[20] + NET gpio_dm0[20]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 988940 4767490 ) N ;
|
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- gpio_dm1[20] + NET gpio_dm1[20]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 998140 4767490 ) N ;
|
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- gpio_dm2[20] + NET gpio_dm2[20]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 967320 4767490 ) N ;
|
|
- gpio_holdover[20] + NET gpio_holdover[20]
|
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+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 964100 4767490 ) N ;
|
|
- gpio_ib_mode_sel[20] + NET gpio_ib_mode_sel[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 948920 4767490 ) N ;
|
|
- gpio_inp_dis[20] + NET gpio_inp_dis[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 982960 4767490 ) N ;
|
|
- gpio_oeb[20] + NET gpio_oeb[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 945700 4767490 ) N ;
|
|
- gpio_out[20] + NET gpio_out[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 961340 4767490 ) N ;
|
|
- gpio_slow_sel[20] + NET gpio_slow_sel[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1007340 4767490 ) N ;
|
|
- gpio_vtrip_sel[20] + NET gpio_vtrip_sel[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 952140 4767490 ) N ;
|
|
- gpio_in[20] + NET gpio_in[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1016540 4767490 ) N ;
|
|
- gpio_analog_en[19] + NET gpio_analog_en[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1250160 4767490 ) N ;
|
|
- gpio_analog_pol[19] + NET gpio_analog_pol[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1243720 4767490 ) N ;
|
|
- gpio_analog_sel[19] + NET gpio_analog_sel[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1228540 4767490 ) N ;
|
|
- gpio_dm0[19] + NET gpio_dm0[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1246940 4767490 ) N ;
|
|
- gpio_dm1[19] + NET gpio_dm1[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1256140 4767490 ) N ;
|
|
- gpio_dm2[19] + NET gpio_dm2[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1225320 4767490 ) N ;
|
|
- gpio_holdover[19] + NET gpio_holdover[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1222100 4767490 ) N ;
|
|
- gpio_ib_mode_sel[19] + NET gpio_ib_mode_sel[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1206920 4767490 ) N ;
|
|
- gpio_inp_dis[19] + NET gpio_inp_dis[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1240960 4767490 ) N ;
|
|
- gpio_oeb[19] + NET gpio_oeb[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1203700 4767490 ) N ;
|
|
- gpio_out[19] + NET gpio_out[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1219340 4767490 ) N ;
|
|
- gpio_in[21] + NET gpio_in[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 759540 4767490 ) N ;
|
|
- gpio_analog_en[22] + NET gpio_analog_en[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 478160 4767490 ) N ;
|
|
- gpio_analog_pol[22] + NET gpio_analog_pol[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 471720 4767490 ) N ;
|
|
- gpio_analog_sel[22] + NET gpio_analog_sel[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 456540 4767490 ) N ;
|
|
- gpio_dm0[22] + NET gpio_dm0[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 474940 4767490 ) N ;
|
|
- gpio_dm1[22] + NET gpio_dm1[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 484140 4767490 ) N ;
|
|
- gpio_dm2[22] + NET gpio_dm2[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 453320 4767490 ) N ;
|
|
- gpio_holdover[22] + NET gpio_holdover[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 450100 4767490 ) N ;
|
|
- gpio_ib_mode_sel[22] + NET gpio_ib_mode_sel[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 434920 4767490 ) N ;
|
|
- gpio_inp_dis[22] + NET gpio_inp_dis[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 468960 4767490 ) N ;
|
|
- gpio_oeb[22] + NET gpio_oeb[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 431700 4767490 ) N ;
|
|
- gpio_out[22] + NET gpio_out[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 447340 4767490 ) N ;
|
|
- gpio_slow_sel[22] + NET gpio_slow_sel[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 493340 4767490 ) N ;
|
|
- gpio_vtrip_sel[22] + NET gpio_vtrip_sel[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 438140 4767490 ) N ;
|
|
- gpio_in[22] + NET gpio_in[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 502540 4767490 ) N ;
|
|
- gpio_analog_en[23] + NET gpio_analog_en[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 221160 4767490 ) N ;
|
|
- gpio_analog_pol[23] + NET gpio_analog_pol[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 214720 4767490 ) N ;
|
|
- gpio_analog_sel[23] + NET gpio_analog_sel[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 199540 4767490 ) N ;
|
|
- gpio_dm0[23] + NET gpio_dm0[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 217940 4767490 ) N ;
|
|
- gpio_dm1[23] + NET gpio_dm1[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 227140 4767490 ) N ;
|
|
- gpio_dm2[23] + NET gpio_dm2[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 196320 4767490 ) N ;
|
|
- gpio_holdover[23] + NET gpio_holdover[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 193100 4767490 ) N ;
|
|
- gpio_ib_mode_sel[23] + NET gpio_ib_mode_sel[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 177920 4767490 ) N ;
|
|
- gpio_inp_dis[23] + NET gpio_inp_dis[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 211960 4767490 ) N ;
|
|
- gpio_oeb[23] + NET gpio_oeb[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 174700 4767490 ) N ;
|
|
- gpio_out[23] + NET gpio_out[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 190340 4767490 ) N ;
|
|
- gpio_slow_sel[23] + NET gpio_slow_sel[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 236340 4767490 ) N ;
|
|
- gpio_vtrip_sel[23] + NET gpio_vtrip_sel[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 181140 4767490 ) N ;
|
|
- gpio_in[23] + NET gpio_in[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 245540 4767490 ) N ;
|
|
- gpio_analog_en[21] + NET gpio_analog_en[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 735160 4767490 ) N ;
|
|
- gpio_analog_pol[21] + NET gpio_analog_pol[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 728720 4767490 ) N ;
|
|
- gpio_analog_sel[21] + NET gpio_analog_sel[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 713540 4767490 ) N ;
|
|
- gpio_dm0[21] + NET gpio_dm0[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 731940 4767490 ) N ;
|
|
- gpio_dm1[21] + NET gpio_dm1[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 741140 4767490 ) N ;
|
|
- gpio_dm2[21] + NET gpio_dm2[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 710320 4767490 ) N ;
|
|
- gpio_holdover[21] + NET gpio_holdover[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 707100 4767490 ) N ;
|
|
- gpio_ib_mode_sel[21] + NET gpio_ib_mode_sel[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 691920 4767490 ) N ;
|
|
- gpio_inp_dis[21] + NET gpio_inp_dis[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 725960 4767490 ) N ;
|
|
- gpio_oeb[21] + NET gpio_oeb[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 688700 4767490 ) N ;
|
|
- gpio_out[21] + NET gpio_out[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 704340 4767490 ) N ;
|
|
- gpio_slow_sel[21] + NET gpio_slow_sel[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 750340 4767490 ) N ;
|
|
- gpio_vtrip_sel[21] + NET gpio_vtrip_sel[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 695140 4767490 ) N ;
|
|
- gpio_in[38] + NET gpio_in[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 726090 -860 ) N ;
|
|
- gpio_slow_sel[38] + NET gpio_slow_sel[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 735290 -860 ) N ;
|
|
- gpio_dm1[38] + NET gpio_dm1[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 744490 -860 ) N ;
|
|
- gpio_dm0[38] + NET gpio_dm0[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 753690 -860 ) N ;
|
|
- gpio_analog_pol[38] + NET gpio_analog_pol[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 756910 -860 ) N ;
|
|
- gpio_analog_en[38] + NET gpio_analog_en[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 750470 -860 ) N ;
|
|
- gpio_inp_dis[38] + NET gpio_inp_dis[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 759670 -860 ) N ;
|
|
- gpio_analog_sel[38] + NET gpio_analog_sel[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 772090 -860 ) N ;
|
|
- gpio_dm2[38] + NET gpio_dm2[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 775310 -860 ) N ;
|
|
- gpio_holdover[38] + NET gpio_holdover[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 778530 -860 ) N ;
|
|
- gpio_out[38] + NET gpio_out[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 781290 -860 ) N ;
|
|
- gpio_vtrip_sel[38] + NET gpio_vtrip_sel[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 790490 -860 ) N ;
|
|
- gpio_ib_mode_sel[38] + NET gpio_ib_mode_sel[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 793710 -860 ) N ;
|
|
- gpio_oeb[38] + NET gpio_oeb[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 796930 -860 ) N ;
|
|
- gpio_in[39] + NET gpio_in[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1269090 -860 ) N ;
|
|
- gpio_slow_sel[39] + NET gpio_slow_sel[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1278290 -860 ) N ;
|
|
- gpio_dm1[39] + NET gpio_dm1[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1287490 -860 ) N ;
|
|
- gpio_dm0[39] + NET gpio_dm0[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1296690 -860 ) N ;
|
|
- gpio_analog_pol[39] + NET gpio_analog_pol[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1299910 -860 ) N ;
|
|
- gpio_analog_en[39] + NET gpio_analog_en[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1293470 -860 ) N ;
|
|
- gpio_inp_dis[39] + NET gpio_inp_dis[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1302670 -860 ) N ;
|
|
- gpio_analog_sel[39] + NET gpio_analog_sel[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1315090 -860 ) N ;
|
|
- gpio_dm2[39] + NET gpio_dm2[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1318310 -860 ) N ;
|
|
- gpio_holdover[39] + NET gpio_holdover[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1321530 -860 ) N ;
|
|
- gpio_out[39] + NET gpio_out[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1324290 -860 ) N ;
|
|
- gpio_vtrip_sel[39] + NET gpio_vtrip_sel[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1333490 -860 ) N ;
|
|
- gpio_ib_mode_sel[39] + NET gpio_ib_mode_sel[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1336710 -860 ) N ;
|
|
- gpio_oeb[39] + NET gpio_oeb[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1339930 -860 ) N ;
|
|
- gpio_in[40] + NET gpio_in[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1543090 -860 ) N ;
|
|
- gpio_slow_sel[40] + NET gpio_slow_sel[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1552290 -860 ) N ;
|
|
- gpio_dm1[40] + NET gpio_dm1[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1561490 -860 ) N ;
|
|
- gpio_dm0[40] + NET gpio_dm0[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1570690 -860 ) N ;
|
|
- gpio_analog_pol[40] + NET gpio_analog_pol[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1573910 -860 ) N ;
|
|
- gpio_analog_en[40] + NET gpio_analog_en[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1567470 -860 ) N ;
|
|
- gpio_inp_dis[40] + NET gpio_inp_dis[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1576670 -860 ) N ;
|
|
- gpio_analog_sel[40] + NET gpio_analog_sel[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1589090 -860 ) N ;
|
|
- gpio_dm2[40] + NET gpio_dm2[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1592310 -860 ) N ;
|
|
- gpio_holdover[40] + NET gpio_holdover[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1595530 -860 ) N ;
|
|
- gpio_out[40] + NET gpio_out[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1598290 -860 ) N ;
|
|
- gpio_vtrip_sel[40] + NET gpio_vtrip_sel[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1607490 -860 ) N ;
|
|
- gpio_ib_mode_sel[40] + NET gpio_ib_mode_sel[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1610710 -860 ) N ;
|
|
- gpio_oeb[40] + NET gpio_oeb[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1613930 -860 ) N ;
|
|
- gpio_in[41] + NET gpio_in[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1817090 -860 ) N ;
|
|
- gpio_slow_sel[41] + NET gpio_slow_sel[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1826290 -860 ) N ;
|
|
- gpio_dm1[41] + NET gpio_dm1[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1835490 -860 ) N ;
|
|
- gpio_dm0[41] + NET gpio_dm0[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1844690 -860 ) N ;
|
|
- gpio_analog_pol[41] + NET gpio_analog_pol[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1847910 -860 ) N ;
|
|
- gpio_analog_en[41] + NET gpio_analog_en[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1841470 -860 ) N ;
|
|
- gpio_inp_dis[41] + NET gpio_inp_dis[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1850670 -860 ) N ;
|
|
- gpio_analog_sel[41] + NET gpio_analog_sel[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1863090 -860 ) N ;
|
|
- gpio_dm2[41] + NET gpio_dm2[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1866310 -860 ) N ;
|
|
- gpio_holdover[41] + NET gpio_holdover[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1869530 -860 ) N ;
|
|
- gpio_out[41] + NET gpio_out[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1872290 -860 ) N ;
|
|
- gpio_vtrip_sel[41] + NET gpio_vtrip_sel[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1881490 -860 ) N ;
|
|
- gpio_ib_mode_sel[41] + NET gpio_ib_mode_sel[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1884710 -860 ) N ;
|
|
- gpio_oeb[41] + NET gpio_oeb[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1887930 -860 ) N ;
|
|
- gpio_in[42] + NET gpio_in[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2091090 -860 ) N ;
|
|
- gpio_slow_sel[42] + NET gpio_slow_sel[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2100290 -860 ) N ;
|
|
- gpio_dm1[42] + NET gpio_dm1[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2109490 -860 ) N ;
|
|
- gpio_dm0[42] + NET gpio_dm0[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2118690 -860 ) N ;
|
|
- gpio_analog_pol[42] + NET gpio_analog_pol[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2121910 -860 ) N ;
|
|
- gpio_analog_en[42] + NET gpio_analog_en[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2115470 -860 ) N ;
|
|
- gpio_inp_dis[42] + NET gpio_inp_dis[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2124670 -860 ) N ;
|
|
- gpio_analog_sel[42] + NET gpio_analog_sel[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2137090 -860 ) N ;
|
|
- gpio_dm2[42] + NET gpio_dm2[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2140310 -860 ) N ;
|
|
- gpio_holdover[42] + NET gpio_holdover[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2143530 -860 ) N ;
|
|
- gpio_out[42] + NET gpio_out[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2146290 -860 ) N ;
|
|
- gpio_vtrip_sel[42] + NET gpio_vtrip_sel[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2155490 -860 ) N ;
|
|
- gpio_ib_mode_sel[42] + NET gpio_ib_mode_sel[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2158710 -860 ) N ;
|
|
- gpio_oeb[42] + NET gpio_oeb[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2161930 -860 ) N ;
|
|
- gpio_in[43] + NET gpio_in[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2365090 -860 ) N ;
|
|
- gpio_slow_sel[43] + NET gpio_slow_sel[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2374290 -860 ) N ;
|
|
- gpio_dm1[43] + NET gpio_dm1[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2383490 -860 ) N ;
|
|
- gpio_dm0[43] + NET gpio_dm0[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2392690 -860 ) N ;
|
|
- gpio_analog_pol[43] + NET gpio_analog_pol[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2395910 -860 ) N ;
|
|
- gpio_analog_en[43] + NET gpio_analog_en[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2389470 -860 ) N ;
|
|
- gpio_inp_dis[43] + NET gpio_inp_dis[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2398670 -860 ) N ;
|
|
- gpio_analog_sel[43] + NET gpio_analog_sel[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2411090 -860 ) N ;
|
|
- gpio_dm2[43] + NET gpio_dm2[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2414310 -860 ) N ;
|
|
- gpio_holdover[43] + NET gpio_holdover[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2417530 -860 ) N ;
|
|
- gpio_out[43] + NET gpio_out[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2420290 -860 ) N ;
|
|
- gpio_ib_mode_sel[43] + NET gpio_ib_mode_sel[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2432710 -860 ) N ;
|
|
- gpio_oeb[43] + NET gpio_oeb[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2435930 -860 ) N ;
|
|
- gpio_in_h[15] + NET gpio_in_h[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2920940 4767490 ) N ;
|
|
- gpio_in_h[16] + NET gpio_in_h[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2411940 4767490 ) N ;
|
|
- gpio_in_h[17] + NET gpio_in_h[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2154940 4767490 ) N ;
|
|
- gpio_in_h[18] + NET gpio_in_h[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1709940 4767490 ) N ;
|
|
- gpio_in_h[19] + NET gpio_in_h[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1200940 4767490 ) N ;
|
|
- gpio_in_h[20] + NET gpio_in_h[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 942940 4767490 ) N ;
|
|
- gpio_in_h[21] + NET gpio_in_h[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 685940 4767490 ) N ;
|
|
- gpio_in_h[22] + NET gpio_in_h[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 428940 4767490 ) N ;
|
|
- gpio_in_h[23] + NET gpio_in_h[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 171940 4767490 ) N ;
|
|
- gpio_in_h[38] + NET gpio_in_h[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 799690 -860 ) N ;
|
|
- gpio_in_h[39] + NET gpio_in_h[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1342690 -860 ) N ;
|
|
- gpio_in_h[40] + NET gpio_in_h[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1616690 -860 ) N ;
|
|
- gpio_in_h[41] + NET gpio_in_h[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 1890690 -860 ) N ;
|
|
- gpio_in_h[42] + NET gpio_in_h[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2164690 -860 ) N ;
|
|
- gpio_in_h[43] + NET gpio_in_h[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 2438690 -860 ) N ;
|
|
- vccd1 + NET vccd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11655 ) ( 1150 11655 ) + PLACED ( 3167480 2125705 ) N ;
|
|
- vdda1 + NET vdda1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 3943870 ) N ;
|
|
- vdda1 + NET vdda1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 2370870 ) N ;
|
|
- vssa1 + NET vssa1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 1929870 ) N ;
|
|
- vssa1 + NET vssa1
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2679760 4767480 ) N ;
|
|
- vssio + NET vssio
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 1468760 4767480 ) N ;
|
|
- vccd2 + NET vccd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11975 ) ( 1150 11975 ) + PLACED ( -850 4412045 ) N ;
|
|
- vddio + NET vddio
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 4150760 ) N ;
|
|
- vssa2 + NET vssa2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 3939760 ) N ;
|
|
- vdda2 + NET vdda2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 2216760 ) N ;
|
|
- vddio + NET vddio
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 352760 ) N ;
|
|
- vssio + NET vssio
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2696870 -850 ) N ;
|
|
- vdda + NET vdda
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2965870 -850 ) N ;
|
|
- analog_noesd_io[8] + NET analog_noesd_io[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 2780710 ) N ;
|
|
- gpio_loopback_one[24] + NET gpio_loopback_one[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 4533370 ) N ;
|
|
- gpio_loopback_one[25] + NET gpio_loopback_one[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3683370 ) N ;
|
|
- gpio_loopback_one[26] + NET gpio_loopback_one[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3468370 ) N ;
|
|
- gpio_loopback_one[27] + NET gpio_loopback_one[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3253370 ) N ;
|
|
- gpio_loopback_one[28] + NET gpio_loopback_one[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3038370 ) N ;
|
|
- gpio_loopback_one[29] + NET gpio_loopback_one[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2823370 ) N ;
|
|
- gpio_loopback_one[30] + NET gpio_loopback_one[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2608370 ) N ;
|
|
- gpio_loopback_one[31] + NET gpio_loopback_one[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2393370 ) N ;
|
|
- gpio_loopback_one[32] + NET gpio_loopback_one[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1748370 ) N ;
|
|
- gpio_loopback_one[33] + NET gpio_loopback_one[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1533370 ) N ;
|
|
- gpio_loopback_one[34] + NET gpio_loopback_one[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1318370 ) N ;
|
|
- gpio_loopback_one[35] + NET gpio_loopback_one[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1103370 ) N ;
|
|
- gpio_loopback_one[36] + NET gpio_loopback_one[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 888370 ) N ;
|
|
- gpio_loopback_one[37] + NET gpio_loopback_one[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 673370 ) N ;
|
|
- gpio_loopback_one[43] + NET gpio_loopback_one[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 2442030 -860 ) N ;
|
|
- gpio_loopback_zero[43] + NET gpio_loopback_zero[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 2463305 -860 ) N ;
|
|
- gpio_loopback_one[42] + NET gpio_loopback_one[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 2168030 -860 ) N ;
|
|
- gpio_loopback_zero[42] + NET gpio_loopback_zero[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 2189020 -860 ) N ;
|
|
- gpio_loopback_one[41] + NET gpio_loopback_one[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1894030 -860 ) N ;
|
|
- gpio_loopback_zero[41] + NET gpio_loopback_zero[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1915020 -860 ) N ;
|
|
- gpio_loopback_one[40] + NET gpio_loopback_one[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1620030 -860 ) N ;
|
|
- gpio_loopback_zero[40] + NET gpio_loopback_zero[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1640955 -860 ) N ;
|
|
- gpio_loopback_one[39] + NET gpio_loopback_one[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1346030 -860 ) N ;
|
|
- gpio_loopback_zero[39] + NET gpio_loopback_zero[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 1366930 -860 ) N ;
|
|
- gpio_loopback_one[38] + NET gpio_loopback_one[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 803030 -860 ) N ;
|
|
- gpio_loopback_zero[38] + NET gpio_loopback_zero[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 819085 -860 ) N ;
|
|
- resetb_l + NET resetb_l
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 550960 -860 ) N ;
|
|
- resetb_h + NET resetb_h
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 498020 -860 ) N ;
|
|
- por_l + NET por_l
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 267035 ) N ;
|
|
- porb_l + NET porb_l
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 268150 ) N ;
|
|
- mask_rev[0] + NET mask_rev[0]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3025540 -860 ) N ;
|
|
- porb_h + NET porb_h
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 265910 ) N ;
|
|
- gpio_loopback_one[15] + NET gpio_loopback_one[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2891640 4767490 ) N ;
|
|
- gpio_loopback_one[16] + NET gpio_loopback_one[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2394640 4767490 ) N ;
|
|
- gpio_loopback_one[17] + NET gpio_loopback_one[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2138640 4767490 ) N ;
|
|
- gpio_loopback_one[18] + NET gpio_loopback_one[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 1693640 4767490 ) N ;
|
|
- gpio_loopback_one[19] + NET gpio_loopback_one[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 1171640 4767490 ) N ;
|
|
- gpio_loopback_one[20] + NET gpio_loopback_one[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 915640 4767490 ) N ;
|
|
- gpio_loopback_one[21] + NET gpio_loopback_one[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 659640 4767490 ) N ;
|
|
- gpio_loopback_one[22] + NET gpio_loopback_one[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 403640 4767490 ) N ;
|
|
- gpio_loopback_one[23] + NET gpio_loopback_one[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 147640 4767490 ) N ;
|
|
- gpio_loopback_one[7] + NET gpio_loopback_one[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 2615180 ) N ;
|
|
- gpio_loopback_one[6] + NET gpio_loopback_one[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1730180 ) N ;
|
|
- gpio_loopback_one[5] + NET gpio_loopback_one[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1505180 ) N ;
|
|
- gpio_loopback_one[4] + NET gpio_loopback_one[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1280180 ) N ;
|
|
- gpio_loopback_one[3] + NET gpio_loopback_one[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1055180 ) N ;
|
|
- gpio_loopback_one[2] + NET gpio_loopback_one[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 830180 ) N ;
|
|
- gpio_loopback_one[1] + NET gpio_loopback_one[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 605180 ) N ;
|
|
- gpio_loopback_one[0] + NET gpio_loopback_one[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 380180 ) N ;
|
|
- mask_rev[4] + NET mask_rev[4]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3030020 -860 ) N ;
|
|
- mask_rev[5] + NET mask_rev[5]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3031140 -860 ) N ;
|
|
- mask_rev[6] + NET mask_rev[6]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3032260 -860 ) N ;
|
|
- mask_rev[7] + NET mask_rev[7]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3033380 -860 ) N ;
|
|
- mask_rev[8] + NET mask_rev[8]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3034500 -860 ) N ;
|
|
- mask_rev[9] + NET mask_rev[9]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3035620 -860 ) N ;
|
|
- mask_rev[10] + NET mask_rev[10]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3036740 -860 ) N ;
|
|
- mask_rev[11] + NET mask_rev[11]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3037860 -860 ) N ;
|
|
- mask_rev[12] + NET mask_rev[12]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3038980 -860 ) N ;
|
|
- mask_rev[13] + NET mask_rev[13]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3040100 -860 ) N ;
|
|
- mask_rev[14] + NET mask_rev[14]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3041220 -860 ) N ;
|
|
- mask_rev[15] + NET mask_rev[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3042340 -860 ) N ;
|
|
- mask_rev[16] + NET mask_rev[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3043460 -860 ) N ;
|
|
- mask_rev[17] + NET mask_rev[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3044580 -860 ) N ;
|
|
- mask_rev[18] + NET mask_rev[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3045700 -860 ) N ;
|
|
- mask_rev[19] + NET mask_rev[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3046820 -860 ) N ;
|
|
- mask_rev[20] + NET mask_rev[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3047940 -860 ) N ;
|
|
- mask_rev[21] + NET mask_rev[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3049060 -860 ) N ;
|
|
- mask_rev[22] + NET mask_rev[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3050180 -860 ) N ;
|
|
- mask_rev[23] + NET mask_rev[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3051300 -860 ) N ;
|
|
- mask_rev[24] + NET mask_rev[24]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3052420 -860 ) N ;
|
|
- mask_rev[25] + NET mask_rev[25]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3053540 -860 ) N ;
|
|
- mask_rev[26] + NET mask_rev[26]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3054660 -860 ) N ;
|
|
- mask_rev[27] + NET mask_rev[27]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3055780 -860 ) N ;
|
|
- mask_rev[28] + NET mask_rev[28]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3056900 -860 ) N ;
|
|
- mask_rev[29] + NET mask_rev[29]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3058020 -860 ) N ;
|
|
- mask_rev[30] + NET mask_rev[30]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3059140 -860 ) N ;
|
|
- mask_rev[31] + NET mask_rev[31]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3060260 -860 ) N ;
|
|
- mask_rev[3] + NET mask_rev[3]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3028900 -860 ) N ;
|
|
- mask_rev[2] + NET mask_rev[2]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3027780 -860 ) N ;
|
|
- mask_rev[1] + NET mask_rev[1]
|
|
+ PORT
|
|
+ LAYER met2 ( -130 -1140 ) ( 130 1140 ) + PLACED ( 3026660 -860 ) N ;
|
|
- gpio_loopback_zero[25] + NET gpio_loopback_zero[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3673370 ) N ;
|
|
- gpio_loopback_zero[27] + NET gpio_loopback_zero[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3243370 ) N ;
|
|
- gpio_loopback_zero[29] + NET gpio_loopback_zero[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2813370 ) N ;
|
|
- gpio_loopback_zero[31] + NET gpio_loopback_zero[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2383370 ) N ;
|
|
- gpio_loopback_zero[33] + NET gpio_loopback_zero[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1523370 ) N ;
|
|
- gpio_loopback_zero[35] + NET gpio_loopback_zero[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1093370 ) N ;
|
|
- gpio_loopback_zero[37] + NET gpio_loopback_zero[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 663370 ) N ;
|
|
- gpio_loopback_zero[24] + NET gpio_loopback_zero[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 4523370 ) N ;
|
|
- gpio_loopback_zero[26] + NET gpio_loopback_zero[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3458370 ) N ;
|
|
- gpio_loopback_zero[28] + NET gpio_loopback_zero[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 3028370 ) N ;
|
|
- gpio_loopback_zero[30] + NET gpio_loopback_zero[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 2598370 ) N ;
|
|
- gpio_loopback_zero[32] + NET gpio_loopback_zero[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1738370 ) N ;
|
|
- gpio_loopback_zero[34] + NET gpio_loopback_zero[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 1308370 ) N ;
|
|
- gpio_loopback_zero[36] + NET gpio_loopback_zero[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -150 ) ( 1150 150 ) + PLACED ( -850 878370 ) N ;
|
|
- gpio_slow_sel[38] + NET gpio_slow_sel[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 735290 -860 ) N ;
|
|
- gpio_in[38] + NET gpio_in[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 726090 -860 ) N ;
|
|
- vssa + NET vssa
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 245870 -850 ) N ;
|
|
- analog_io[0] + NET analog_io[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 306510 ) N ;
|
|
- analog_noesd_io[0] + NET analog_noesd_io[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 315710 ) N ;
|
|
- analog_noesd_io[1] + NET analog_noesd_io[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 541710 ) N ;
|
|
- analog_io[1] + NET analog_io[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 532510 ) N ;
|
|
- analog_io[2] + NET analog_io[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 757510 ) N ;
|
|
- analog_noesd_io[2] + NET analog_noesd_io[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 766710 ) N ;
|
|
- analog_io[3] + NET analog_io[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 983510 ) N ;
|
|
- analog_noesd_io[3] + NET analog_noesd_io[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 992710 ) N ;
|
|
- analog_io[4] + NET analog_io[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 1208510 ) N ;
|
|
- analog_noesd_io[4] + NET analog_noesd_io[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 1217710 ) N ;
|
|
- analog_io[5] + NET analog_io[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 1433510 ) N ;
|
|
- analog_noesd_io[5] + NET analog_noesd_io[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 1442710 ) N ;
|
|
- analog_io[6] + NET analog_io[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 1659510 ) N ;
|
|
- analog_noesd_io[6] + NET analog_noesd_io[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 1668710 ) N ;
|
|
- analog_io[7] + NET analog_io[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 2545510 ) N ;
|
|
- analog_noesd_io[7] + NET analog_noesd_io[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 2554710 ) N ;
|
|
- analog_io[8] + NET analog_io[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 2771510 ) N ;
|
|
- analog_io[9] + NET analog_io[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 2996510 ) N ;
|
|
- analog_noesd_io[9] + NET analog_noesd_io[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 3005710 ) N ;
|
|
- analog_io[10] + NET analog_io[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 3222510 ) N ;
|
|
- analog_noesd_io[10] + NET analog_noesd_io[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 3231710 ) N ;
|
|
- analog_io[11] + NET analog_io[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 3447510 ) N ;
|
|
- analog_noesd_io[11] + NET analog_noesd_io[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 3456710 ) N ;
|
|
- analog_io[12] + NET analog_io[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 3672510 ) N ;
|
|
- analog_io[13] + NET analog_io[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 4118510 ) N ;
|
|
- analog_io[14] + NET analog_io[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( 3167480 4564510 ) N ;
|
|
- analog_noesd_io[12] + NET analog_noesd_io[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 3681710 ) N ;
|
|
- analog_noesd_io[13] + NET analog_noesd_io[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 4127710 ) N ;
|
|
- analog_noesd_io[14] + NET analog_noesd_io[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( 3167480 4573710 ) N ;
|
|
- analog_io[15] + NET analog_io[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 2982120 4767490 ) N ;
|
|
- analog_io[16] + NET analog_io[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 2473120 4767490 ) N ;
|
|
- analog_io[17] + NET analog_io[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 2216120 4767490 ) N ;
|
|
- analog_io[18] + NET analog_io[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1771120 4767490 ) N ;
|
|
- analog_io[19] + NET analog_io[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1262120 4767490 ) N ;
|
|
- analog_io[20] + NET analog_io[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1004120 4767490 ) N ;
|
|
- analog_io[21] + NET analog_io[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 747120 4767490 ) N ;
|
|
- analog_io[22] + NET analog_io[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 490120 4767490 ) N ;
|
|
- analog_io[23] + NET analog_io[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 233120 4767490 ) N ;
|
|
- analog_noesd_io[15] + NET analog_noesd_io[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 2972920 4767490 ) N ;
|
|
- analog_noesd_io[16] + NET analog_noesd_io[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 2463920 4767490 ) N ;
|
|
- analog_noesd_io[17] + NET analog_noesd_io[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 2206920 4767490 ) N ;
|
|
- analog_noesd_io[18] + NET analog_noesd_io[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 1761920 4767490 ) N ;
|
|
- analog_noesd_io[19] + NET analog_noesd_io[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 1252920 4767490 ) N ;
|
|
- analog_noesd_io[20] + NET analog_noesd_io[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 994920 4767490 ) N ;
|
|
- analog_noesd_io[21] + NET analog_noesd_io[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 737920 4767490 ) N ;
|
|
- analog_noesd_io[22] + NET analog_noesd_io[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 480920 4767490 ) N ;
|
|
- analog_noesd_io[23] + NET analog_noesd_io[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 223920 4767490 ) N ;
|
|
- analog_io[25] + NET analog_io[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 3774120 ) N ;
|
|
- analog_io[26] + NET analog_io[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 3558120 ) N ;
|
|
- analog_io[27] + NET analog_io[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 3342120 ) N ;
|
|
- analog_io[28] + NET analog_io[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 3126120 ) N ;
|
|
- analog_io[29] + NET analog_io[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 2910120 ) N ;
|
|
- analog_io[30] + NET analog_io[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 2694120 ) N ;
|
|
- analog_io[31] + NET analog_io[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 2478120 ) N ;
|
|
- analog_io[32] + NET analog_io[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 1840120 ) N ;
|
|
- analog_io[33] + NET analog_io[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 1624120 ) N ;
|
|
- analog_io[34] + NET analog_io[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 1408120 ) N ;
|
|
- analog_io[35] + NET analog_io[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 1192120 ) N ;
|
|
- analog_io[36] + NET analog_io[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 976120 ) N ;
|
|
- analog_io[37] + NET analog_io[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 760120 ) N ;
|
|
- analog_noesd_io[25] + NET analog_noesd_io[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 3764920 ) N ;
|
|
- analog_noesd_io[26] + NET analog_noesd_io[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 3548920 ) N ;
|
|
- analog_noesd_io[27] + NET analog_noesd_io[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 3332920 ) N ;
|
|
- analog_noesd_io[28] + NET analog_noesd_io[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 3116920 ) N ;
|
|
- analog_noesd_io[29] + NET analog_noesd_io[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 2900920 ) N ;
|
|
- analog_noesd_io[30] + NET analog_noesd_io[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 2684920 ) N ;
|
|
- analog_noesd_io[32] + NET analog_noesd_io[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 1830920 ) N ;
|
|
- analog_noesd_io[33] + NET analog_noesd_io[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 1614920 ) N ;
|
|
- analog_noesd_io[34] + NET analog_noesd_io[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 1398920 ) N ;
|
|
- analog_noesd_io[35] + NET analog_noesd_io[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 1182920 ) N ;
|
|
- analog_noesd_io[36] + NET analog_noesd_io[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 966920 ) N ;
|
|
- analog_noesd_io[37] + NET analog_noesd_io[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 750920 ) N ;
|
|
- analog_io[39] + NET analog_io[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1281510 -860 ) N ;
|
|
- analog_io[40] + NET analog_io[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1555510 -860 ) N ;
|
|
- analog_io[41] + NET analog_io[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 1829510 -860 ) N ;
|
|
- analog_io[42] + NET analog_io[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 2103510 -860 ) N ;
|
|
- analog_io[43] + NET analog_io[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 2377510 -860 ) N ;
|
|
- analog_noesd_io[39] + NET analog_noesd_io[39]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 1290710 -860 ) N ;
|
|
- analog_noesd_io[40] + NET analog_noesd_io[40]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 1564710 -860 ) N ;
|
|
- analog_noesd_io[41] + NET analog_noesd_io[41]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 1838710 -860 ) N ;
|
|
- analog_noesd_io[42] + NET analog_noesd_io[42]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 2112710 -860 ) N ;
|
|
- analog_noesd_io[43] + NET analog_noesd_io[43]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 2386710 -860 ) N ;
|
|
- analog_noesd_io[38] + NET analog_noesd_io[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -535 -1140 ) ( 535 1140 ) + PLACED ( 747710 -860 ) N ;
|
|
- analog_io[38] + NET analog_io[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -320 -1140 ) ( 320 1140 ) + PLACED ( 738510 -860 ) N ;
|
|
- gpio_dm1[38] + NET gpio_dm1[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 744490 -860 ) N ;
|
|
- gpio_dm0[38] + NET gpio_dm0[38]
|
|
+ PORT
|
|
+ LAYER met2 ( -140 -1140 ) ( 140 1140 ) + PLACED ( 753690 -860 ) N ;
|
|
- analog_noesd_io[31] + NET analog_noesd_io[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 2468920 ) N ;
|
|
- vssa1 + NET vssa1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 1879980 ) N ;
|
|
- vssd1 + NET vssd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11975 ) ( 1150 11975 ) + PLACED ( 3167480 2100585 ) N ;
|
|
- vssd1 + NET vssd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -12000 ) ( 1150 12000 ) + PLACED ( 3167480 2150810 ) N ;
|
|
- vdda1 + NET vdda1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 2320970 ) N ;
|
|
- gpio_loopback_one[8] + NET gpio_loopback_one[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 2840185 ) N ;
|
|
- gpio_loopback_one[9] + NET gpio_loopback_one[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3065185 ) N ;
|
|
- gpio_loopback_one[10] + NET gpio_loopback_one[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3290185 ) N ;
|
|
- gpio_loopback_one[11] + NET gpio_loopback_one[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3515185 ) N ;
|
|
- gpio_loopback_one[12] + NET gpio_loopback_one[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3740185 ) N ;
|
|
- vdda1 + NET vdda1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( 3167480 3893980 ) N ;
|
|
- gpio_loopback_one[13] + NET gpio_loopback_one[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 4185185 ) N ;
|
|
- gpio_loopback_one[14] + NET gpio_loopback_one[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 4635185 ) N ;
|
|
- vssa1 + NET vssa1
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2729660 4767480 ) N ;
|
|
- vssio + NET vssio
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 1518660 4767480 ) N ;
|
|
- vssd2 + NET vssd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11655 ) ( 1150 11655 ) + PLACED ( -850 4386925 ) N ;
|
|
- vccd2 + NET vccd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -12000 ) ( 1150 12000 ) + PLACED ( -850 4361820 ) N ;
|
|
- vddio + NET vddio
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 4200660 ) N ;
|
|
- vssa2 + NET vssa2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 3989660 ) N ;
|
|
- gpio_in[25] + NET gpio_in[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3786535 ) N ;
|
|
- gpio_slow_sel[25] + NET gpio_slow_sel[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3777335 ) N ;
|
|
- gpio_dm1[25] + NET gpio_dm1[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3768135 ) N ;
|
|
- gpio_analog_en[25] + NET gpio_analog_en[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3762155 ) N ;
|
|
- gpio_dm0[25] + NET gpio_dm0[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3758935 ) N ;
|
|
- gpio_analog_pol[25] + NET gpio_analog_pol[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3755715 ) N ;
|
|
- gpio_inp_dis[25] + NET gpio_inp_dis[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3752955 ) N ;
|
|
- gpio_analog_sel[25] + NET gpio_analog_sel[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3740535 ) N ;
|
|
- gpio_dm2[25] + NET gpio_dm2[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3737315 ) N ;
|
|
- gpio_holdover[25] + NET gpio_holdover[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3734095 ) N ;
|
|
- gpio_out[25] + NET gpio_out[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3731335 ) N ;
|
|
- gpio_vtrip_sel[25] + NET gpio_vtrip_sel[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3722135 ) N ;
|
|
- gpio_ib_mode_sel[25] + NET gpio_ib_mode_sel[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3718915 ) N ;
|
|
- gpio_oeb[25] + NET gpio_oeb[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3715695 ) N ;
|
|
- gpio_in_h[25] + NET gpio_in_h[25]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3712935 ) N ;
|
|
- gpio_in[26] + NET gpio_in[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3570535 ) N ;
|
|
- gpio_slow_sel[26] + NET gpio_slow_sel[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3561335 ) N ;
|
|
- gpio_dm1[26] + NET gpio_dm1[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3552135 ) N ;
|
|
- gpio_analog_en[26] + NET gpio_analog_en[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3546155 ) N ;
|
|
- gpio_dm0[26] + NET gpio_dm0[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3542935 ) N ;
|
|
- gpio_analog_pol[26] + NET gpio_analog_pol[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3539715 ) N ;
|
|
- gpio_inp_dis[26] + NET gpio_inp_dis[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3536955 ) N ;
|
|
- gpio_analog_sel[26] + NET gpio_analog_sel[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3524535 ) N ;
|
|
- gpio_dm2[26] + NET gpio_dm2[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3521315 ) N ;
|
|
- gpio_holdover[26] + NET gpio_holdover[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3518095 ) N ;
|
|
- gpio_out[26] + NET gpio_out[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3515335 ) N ;
|
|
- gpio_vtrip_sel[26] + NET gpio_vtrip_sel[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3506135 ) N ;
|
|
- gpio_ib_mode_sel[26] + NET gpio_ib_mode_sel[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3502915 ) N ;
|
|
- gpio_oeb[26] + NET gpio_oeb[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3499695 ) N ;
|
|
- gpio_in_h[26] + NET gpio_in_h[26]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3496935 ) N ;
|
|
- gpio_vtrip_sel[37] + NET gpio_vtrip_sel[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 708135 ) N ;
|
|
- gpio_analog_en[37] + NET gpio_analog_en[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 748155 ) N ;
|
|
- gpio_analog_pol[37] + NET gpio_analog_pol[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 741715 ) N ;
|
|
- gpio_analog_sel[37] + NET gpio_analog_sel[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 726535 ) N ;
|
|
- gpio_dm0[37] + NET gpio_dm0[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 744935 ) N ;
|
|
- gpio_dm2[37] + NET gpio_dm2[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 723315 ) N ;
|
|
- gpio_holdover[37] + NET gpio_holdover[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 720095 ) N ;
|
|
- gpio_ib_mode_sel[37] + NET gpio_ib_mode_sel[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 704915 ) N ;
|
|
- gpio_oeb[37] + NET gpio_oeb[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 701695 ) N ;
|
|
- gpio_out[37] + NET gpio_out[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 717335 ) N ;
|
|
- gpio_inp_dis[37] + NET gpio_inp_dis[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 738955 ) N ;
|
|
- gpio_in_h[37] + NET gpio_in_h[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 698935 ) N ;
|
|
- gpio_dm1[37] + NET gpio_dm1[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 754135 ) N ;
|
|
- gpio_slow_sel[37] + NET gpio_slow_sel[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 763335 ) N ;
|
|
- gpio_in[37] + NET gpio_in[37]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 772535 ) N ;
|
|
- gpio_dm2[36] + NET gpio_dm2[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 939315 ) N ;
|
|
- gpio_holdover[36] + NET gpio_holdover[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 936095 ) N ;
|
|
- gpio_ib_mode_sel[36] + NET gpio_ib_mode_sel[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 920915 ) N ;
|
|
- gpio_inp_dis[36] + NET gpio_inp_dis[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 954955 ) N ;
|
|
- gpio_oeb[36] + NET gpio_oeb[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 917695 ) N ;
|
|
- gpio_out[36] + NET gpio_out[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 933335 ) N ;
|
|
- gpio_vtrip_sel[36] + NET gpio_vtrip_sel[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 924135 ) N ;
|
|
- gpio_analog_en[36] + NET gpio_analog_en[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 964155 ) N ;
|
|
- gpio_analog_pol[36] + NET gpio_analog_pol[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 957715 ) N ;
|
|
- gpio_analog_sel[36] + NET gpio_analog_sel[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 942535 ) N ;
|
|
- gpio_dm0[36] + NET gpio_dm0[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 960935 ) N ;
|
|
- gpio_in_h[36] + NET gpio_in_h[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 914935 ) N ;
|
|
- gpio_dm1[36] + NET gpio_dm1[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 970135 ) N ;
|
|
- gpio_slow_sel[36] + NET gpio_slow_sel[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 979335 ) N ;
|
|
- gpio_in[36] + NET gpio_in[36]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 988535 ) N ;
|
|
- gpio_analog_en[35] + NET gpio_analog_en[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1180155 ) N ;
|
|
- gpio_analog_pol[35] + NET gpio_analog_pol[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1173715 ) N ;
|
|
- gpio_analog_sel[35] + NET gpio_analog_sel[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1158535 ) N ;
|
|
- gpio_dm0[35] + NET gpio_dm0[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1176935 ) N ;
|
|
- gpio_dm2[35] + NET gpio_dm2[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1155315 ) N ;
|
|
- gpio_holdover[35] + NET gpio_holdover[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1152095 ) N ;
|
|
- gpio_ib_mode_sel[35] + NET gpio_ib_mode_sel[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1136915 ) N ;
|
|
- gpio_inp_dis[35] + NET gpio_inp_dis[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1170955 ) N ;
|
|
- gpio_oeb[35] + NET gpio_oeb[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1133695 ) N ;
|
|
- gpio_out[35] + NET gpio_out[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1149335 ) N ;
|
|
- gpio_vtrip_sel[35] + NET gpio_vtrip_sel[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1140135 ) N ;
|
|
- gpio_in_h[35] + NET gpio_in_h[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1130935 ) N ;
|
|
- gpio_dm1[35] + NET gpio_dm1[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1186135 ) N ;
|
|
- gpio_slow_sel[35] + NET gpio_slow_sel[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1195335 ) N ;
|
|
- gpio_in[35] + NET gpio_in[35]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1204535 ) N ;
|
|
- gpio_analog_en[34] + NET gpio_analog_en[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1396155 ) N ;
|
|
- gpio_analog_pol[34] + NET gpio_analog_pol[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1389715 ) N ;
|
|
- gpio_analog_sel[34] + NET gpio_analog_sel[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1374535 ) N ;
|
|
- gpio_dm0[34] + NET gpio_dm0[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1392935 ) N ;
|
|
- gpio_dm2[34] + NET gpio_dm2[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1371315 ) N ;
|
|
- gpio_holdover[34] + NET gpio_holdover[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1368095 ) N ;
|
|
- gpio_ib_mode_sel[34] + NET gpio_ib_mode_sel[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1352915 ) N ;
|
|
- gpio_inp_dis[34] + NET gpio_inp_dis[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1386955 ) N ;
|
|
- gpio_oeb[34] + NET gpio_oeb[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1349695 ) N ;
|
|
- gpio_out[34] + NET gpio_out[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1365335 ) N ;
|
|
- gpio_vtrip_sel[34] + NET gpio_vtrip_sel[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1356135 ) N ;
|
|
- gpio_in_h[34] + NET gpio_in_h[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1346935 ) N ;
|
|
- gpio_dm1[34] + NET gpio_dm1[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1402135 ) N ;
|
|
- gpio_slow_sel[34] + NET gpio_slow_sel[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1411335 ) N ;
|
|
- gpio_in[34] + NET gpio_in[34]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1420535 ) N ;
|
|
- gpio_analog_en[33] + NET gpio_analog_en[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1612155 ) N ;
|
|
- gpio_analog_sel[33] + NET gpio_analog_sel[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1590535 ) N ;
|
|
- gpio_dm2[33] + NET gpio_dm2[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1587315 ) N ;
|
|
- gpio_dm0[33] + NET gpio_dm0[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1608935 ) N ;
|
|
- gpio_holdover[33] + NET gpio_holdover[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1584095 ) N ;
|
|
- gpio_ib_mode_sel[33] + NET gpio_ib_mode_sel[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1568915 ) N ;
|
|
- gpio_inp_dis[33] + NET gpio_inp_dis[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1602955 ) N ;
|
|
- gpio_oeb[33] + NET gpio_oeb[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1565695 ) N ;
|
|
- gpio_out[33] + NET gpio_out[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1581335 ) N ;
|
|
- gpio_vtrip_sel[33] + NET gpio_vtrip_sel[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1572135 ) N ;
|
|
- gpio_in_h[33] + NET gpio_in_h[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1562935 ) N ;
|
|
- gpio_analog_pol[33] + NET gpio_analog_pol[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1605715 ) N ;
|
|
- gpio_dm1[33] + NET gpio_dm1[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1618135 ) N ;
|
|
- gpio_slow_sel[33] + NET gpio_slow_sel[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1627335 ) N ;
|
|
- gpio_in[33] + NET gpio_in[33]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1636535 ) N ;
|
|
- gpio_analog_en[32] + NET gpio_analog_en[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1828155 ) N ;
|
|
- gpio_analog_pol[32] + NET gpio_analog_pol[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1821715 ) N ;
|
|
- gpio_analog_sel[32] + NET gpio_analog_sel[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1806535 ) N ;
|
|
- gpio_dm0[32] + NET gpio_dm0[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1824935 ) N ;
|
|
- gpio_dm2[32] + NET gpio_dm2[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1803315 ) N ;
|
|
- gpio_holdover[32] + NET gpio_holdover[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1800095 ) N ;
|
|
- gpio_ib_mode_sel[32] + NET gpio_ib_mode_sel[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1784915 ) N ;
|
|
- gpio_inp_dis[32] + NET gpio_inp_dis[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1818955 ) N ;
|
|
- gpio_oeb[32] + NET gpio_oeb[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1781695 ) N ;
|
|
- gpio_out[32] + NET gpio_out[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1797335 ) N ;
|
|
- gpio_vtrip_sel[32] + NET gpio_vtrip_sel[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1788135 ) N ;
|
|
- gpio_in_h[32] + NET gpio_in_h[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1778935 ) N ;
|
|
- gpio_dm1[32] + NET gpio_dm1[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1834135 ) N ;
|
|
- gpio_slow_sel[32] + NET gpio_slow_sel[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1843335 ) N ;
|
|
- gpio_in[32] + NET gpio_in[32]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 1852535 ) N ;
|
|
- gpio_analog_en[31] + NET gpio_analog_en[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2466155 ) N ;
|
|
- gpio_analog_pol[31] + NET gpio_analog_pol[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2459715 ) N ;
|
|
- gpio_analog_sel[31] + NET gpio_analog_sel[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2444535 ) N ;
|
|
- gpio_dm0[31] + NET gpio_dm0[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2462935 ) N ;
|
|
- gpio_dm2[31] + NET gpio_dm2[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2441315 ) N ;
|
|
- gpio_holdover[31] + NET gpio_holdover[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2438095 ) N ;
|
|
- gpio_ib_mode_sel[31] + NET gpio_ib_mode_sel[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2422915 ) N ;
|
|
- gpio_inp_dis[31] + NET gpio_inp_dis[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2456955 ) N ;
|
|
- gpio_oeb[31] + NET gpio_oeb[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2419695 ) N ;
|
|
- gpio_out[31] + NET gpio_out[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2435335 ) N ;
|
|
- gpio_vtrip_sel[31] + NET gpio_vtrip_sel[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2426135 ) N ;
|
|
- gpio_in_h[31] + NET gpio_in_h[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2416935 ) N ;
|
|
- gpio_dm1[31] + NET gpio_dm1[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2472135 ) N ;
|
|
- gpio_slow_sel[31] + NET gpio_slow_sel[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2481335 ) N ;
|
|
- gpio_in[31] + NET gpio_in[31]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2490535 ) N ;
|
|
- gpio_dm0[30] + NET gpio_dm0[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2678935 ) N ;
|
|
- gpio_dm2[30] + NET gpio_dm2[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2657315 ) N ;
|
|
- gpio_holdover[30] + NET gpio_holdover[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2654095 ) N ;
|
|
- gpio_ib_mode_sel[30] + NET gpio_ib_mode_sel[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2638915 ) N ;
|
|
- gpio_inp_dis[30] + NET gpio_inp_dis[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2672955 ) N ;
|
|
- gpio_oeb[30] + NET gpio_oeb[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2635695 ) N ;
|
|
- gpio_out[30] + NET gpio_out[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2651335 ) N ;
|
|
- gpio_vtrip_sel[30] + NET gpio_vtrip_sel[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2642135 ) N ;
|
|
- gpio_analog_en[30] + NET gpio_analog_en[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2682155 ) N ;
|
|
- gpio_analog_pol[30] + NET gpio_analog_pol[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2675715 ) N ;
|
|
- gpio_analog_sel[30] + NET gpio_analog_sel[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2660535 ) N ;
|
|
- gpio_in_h[30] + NET gpio_in_h[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2632935 ) N ;
|
|
- gpio_dm1[30] + NET gpio_dm1[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2688135 ) N ;
|
|
- gpio_slow_sel[30] + NET gpio_slow_sel[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2697335 ) N ;
|
|
- gpio_in[30] + NET gpio_in[30]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2706535 ) N ;
|
|
- gpio_analog_sel[29] + NET gpio_analog_sel[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2876535 ) N ;
|
|
- gpio_dm2[29] + NET gpio_dm2[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2873315 ) N ;
|
|
- gpio_holdover[29] + NET gpio_holdover[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2870095 ) N ;
|
|
- gpio_ib_mode_sel[29] + NET gpio_ib_mode_sel[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2854915 ) N ;
|
|
- gpio_oeb[29] + NET gpio_oeb[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2851695 ) N ;
|
|
- gpio_out[29] + NET gpio_out[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2867335 ) N ;
|
|
- gpio_vtrip_sel[29] + NET gpio_vtrip_sel[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2858135 ) N ;
|
|
- gpio_in_h[29] + NET gpio_in_h[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2848935 ) N ;
|
|
- gpio_analog_en[29] + NET gpio_analog_en[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2898155 ) N ;
|
|
- gpio_analog_pol[29] + NET gpio_analog_pol[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2891715 ) N ;
|
|
- gpio_dm0[29] + NET gpio_dm0[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2894935 ) N ;
|
|
- gpio_inp_dis[29] + NET gpio_inp_dis[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2888955 ) N ;
|
|
- gpio_dm1[29] + NET gpio_dm1[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2904135 ) N ;
|
|
- gpio_slow_sel[29] + NET gpio_slow_sel[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2913335 ) N ;
|
|
- gpio_in[29] + NET gpio_in[29]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 2922535 ) N ;
|
|
- gpio_analog_en[28] + NET gpio_analog_en[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3114155 ) N ;
|
|
- gpio_analog_pol[28] + NET gpio_analog_pol[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3107715 ) N ;
|
|
- gpio_analog_sel[28] + NET gpio_analog_sel[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3092535 ) N ;
|
|
- gpio_dm0[28] + NET gpio_dm0[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3110935 ) N ;
|
|
- gpio_dm2[28] + NET gpio_dm2[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3089315 ) N ;
|
|
- gpio_holdover[28] + NET gpio_holdover[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3086095 ) N ;
|
|
- gpio_ib_mode_sel[28] + NET gpio_ib_mode_sel[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3070915 ) N ;
|
|
- gpio_inp_dis[28] + NET gpio_inp_dis[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3104955 ) N ;
|
|
- gpio_oeb[28] + NET gpio_oeb[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3067695 ) N ;
|
|
- gpio_out[28] + NET gpio_out[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3083335 ) N ;
|
|
- gpio_vtrip_sel[28] + NET gpio_vtrip_sel[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3074135 ) N ;
|
|
- gpio_in_h[28] + NET gpio_in_h[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3064935 ) N ;
|
|
- gpio_dm1[28] + NET gpio_dm1[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3120135 ) N ;
|
|
- gpio_slow_sel[28] + NET gpio_slow_sel[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3129335 ) N ;
|
|
- gpio_in[28] + NET gpio_in[28]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3138535 ) N ;
|
|
- gpio_analog_en[27] + NET gpio_analog_en[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3330155 ) N ;
|
|
- gpio_analog_pol[27] + NET gpio_analog_pol[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3323715 ) N ;
|
|
- gpio_analog_sel[27] + NET gpio_analog_sel[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3308535 ) N ;
|
|
- gpio_dm0[27] + NET gpio_dm0[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3326935 ) N ;
|
|
- gpio_dm2[27] + NET gpio_dm2[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3305315 ) N ;
|
|
- gpio_holdover[27] + NET gpio_holdover[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3302095 ) N ;
|
|
- gpio_ib_mode_sel[27] + NET gpio_ib_mode_sel[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3286915 ) N ;
|
|
- gpio_inp_dis[27] + NET gpio_inp_dis[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3320955 ) N ;
|
|
- gpio_oeb[27] + NET gpio_oeb[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3283695 ) N ;
|
|
- gpio_out[27] + NET gpio_out[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3299335 ) N ;
|
|
- gpio_vtrip_sel[27] + NET gpio_vtrip_sel[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3290135 ) N ;
|
|
- gpio_in_h[27] + NET gpio_in_h[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3280935 ) N ;
|
|
- gpio_dm1[27] + NET gpio_dm1[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3336135 ) N ;
|
|
- gpio_slow_sel[27] + NET gpio_slow_sel[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3345335 ) N ;
|
|
- gpio_in[27] + NET gpio_in[27]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 3354535 ) N ;
|
|
- vdda2 + NET vdda2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 2266650 ) N ;
|
|
- vssd2 + NET vssd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11975 ) ( 1150 11975 ) + PLACED ( -850 2056045 ) N ;
|
|
- vccd2 + NET vccd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11630 ) ( 1150 11630 ) + PLACED ( -850 2030940 ) N ;
|
|
- vssd2 + NET vssd2
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -12000 ) ( 1150 12000 ) + PLACED ( -850 2005810 ) N ;
|
|
- vddio + NET vddio
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11950 ) ( 1150 11950 ) + PLACED ( -850 402650 ) N ;
|
|
- vccd + NET vccd
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11975 ) ( 1150 11975 ) + PLACED ( -850 192045 ) N ;
|
|
- vccd + NET vccd
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -12000 ) ( 1150 12000 ) + PLACED ( -850 141810 ) N ;
|
|
- vssa + NET vssa
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 195980 -850 ) N ;
|
|
- vssd + NET vssd
|
|
+ PORT
|
|
+ LAYER met3 ( -11575 -1150 ) ( 11575 1150 ) + PLACED ( 1007995 -850 ) N ;
|
|
- vssd + NET vssd
|
|
+ PORT
|
|
+ LAYER met3 ( -12000 -1150 ) ( 12000 1150 ) + PLACED ( 1057820 -850 ) N ;
|
|
- vssio + NET vssio
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2646980 -850 ) N ;
|
|
- vdda + NET vdda
|
|
+ PORT
|
|
+ LAYER met3 ( -11950 -1150 ) ( 11950 1150 ) + PLACED ( 2915980 -850 ) N ;
|
|
- gpio_loopback_zero[14] + NET gpio_loopback_zero[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 4645185 ) N ;
|
|
- gpio_loopback_zero[13] + NET gpio_loopback_zero[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 4195185 ) N ;
|
|
- gpio_loopback_zero[12] + NET gpio_loopback_zero[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3750185 ) N ;
|
|
- gpio_loopback_zero[11] + NET gpio_loopback_zero[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3525185 ) N ;
|
|
- gpio_loopback_zero[10] + NET gpio_loopback_zero[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3300185 ) N ;
|
|
- gpio_loopback_zero[9] + NET gpio_loopback_zero[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 3075185 ) N ;
|
|
- gpio_loopback_zero[8] + NET gpio_loopback_zero[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 2850185 ) N ;
|
|
- gpio_loopback_zero[7] + NET gpio_loopback_zero[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 2625185 ) N ;
|
|
- gpio_loopback_zero[6] + NET gpio_loopback_zero[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1740185 ) N ;
|
|
- gpio_loopback_zero[5] + NET gpio_loopback_zero[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1515185 ) N ;
|
|
- gpio_loopback_zero[4] + NET gpio_loopback_zero[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1290185 ) N ;
|
|
- gpio_loopback_zero[3] + NET gpio_loopback_zero[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 1065185 ) N ;
|
|
- gpio_loopback_zero[2] + NET gpio_loopback_zero[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 840185 ) N ;
|
|
- gpio_loopback_zero[1] + NET gpio_loopback_zero[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 615185 ) N ;
|
|
- gpio_loopback_zero[0] + NET gpio_loopback_zero[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -155 ) ( 1150 155 ) + PLACED ( 3167480 390185 ) N ;
|
|
- gpio_slow_sel[0] + NET gpio_slow_sel[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 303295 ) N ;
|
|
- gpio_in[0] + NET gpio_in[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 294095 ) N ;
|
|
- gpio_dm1[0] + NET gpio_dm1[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 312495 ) N ;
|
|
- gpio_analog_en[0] + NET gpio_analog_en[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 318475 ) N ;
|
|
- gpio_analog_pol[0] + NET gpio_analog_pol[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 324915 ) N ;
|
|
- gpio_analog_sel[0] + NET gpio_analog_sel[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 340095 ) N ;
|
|
- gpio_dm0[0] + NET gpio_dm0[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 321695 ) N ;
|
|
- gpio_dm2[0] + NET gpio_dm2[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 343315 ) N ;
|
|
- gpio_holdover[0] + NET gpio_holdover[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 346535 ) N ;
|
|
- gpio_ib_mode_sel[0] + NET gpio_ib_mode_sel[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 361715 ) N ;
|
|
- gpio_inp_dis[0] + NET gpio_inp_dis[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 327675 ) N ;
|
|
- gpio_oeb[0] + NET gpio_oeb[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 364935 ) N ;
|
|
- gpio_out[0] + NET gpio_out[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 349295 ) N ;
|
|
- gpio_vtrip_sel[0] + NET gpio_vtrip_sel[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 358495 ) N ;
|
|
- gpio_in_h[0] + NET gpio_in_h[0]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 367695 ) N ;
|
|
- gpio_slow_sel[1] + NET gpio_slow_sel[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 529295 ) N ;
|
|
- gpio_in[1] + NET gpio_in[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 520095 ) N ;
|
|
- gpio_dm1[1] + NET gpio_dm1[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 538495 ) N ;
|
|
- gpio_analog_en[1] + NET gpio_analog_en[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 544475 ) N ;
|
|
- gpio_analog_pol[1] + NET gpio_analog_pol[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 550915 ) N ;
|
|
- gpio_analog_sel[1] + NET gpio_analog_sel[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 566095 ) N ;
|
|
- gpio_dm0[1] + NET gpio_dm0[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 547695 ) N ;
|
|
- gpio_dm2[1] + NET gpio_dm2[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 569315 ) N ;
|
|
- gpio_holdover[1] + NET gpio_holdover[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 572535 ) N ;
|
|
- gpio_ib_mode_sel[1] + NET gpio_ib_mode_sel[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 587715 ) N ;
|
|
- gpio_inp_dis[1] + NET gpio_inp_dis[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 553675 ) N ;
|
|
- gpio_oeb[1] + NET gpio_oeb[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 590935 ) N ;
|
|
- gpio_out[1] + NET gpio_out[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 575295 ) N ;
|
|
- gpio_vtrip_sel[1] + NET gpio_vtrip_sel[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 584495 ) N ;
|
|
- gpio_in_h[1] + NET gpio_in_h[1]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 593695 ) N ;
|
|
- gpio_slow_sel[2] + NET gpio_slow_sel[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 754295 ) N ;
|
|
- gpio_in[2] + NET gpio_in[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 745095 ) N ;
|
|
- gpio_dm1[2] + NET gpio_dm1[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 763495 ) N ;
|
|
- gpio_analog_en[2] + NET gpio_analog_en[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 769475 ) N ;
|
|
- gpio_analog_pol[2] + NET gpio_analog_pol[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 775915 ) N ;
|
|
- gpio_analog_sel[2] + NET gpio_analog_sel[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 791095 ) N ;
|
|
- gpio_dm0[2] + NET gpio_dm0[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 772695 ) N ;
|
|
- gpio_dm2[2] + NET gpio_dm2[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 794315 ) N ;
|
|
- gpio_holdover[2] + NET gpio_holdover[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 797535 ) N ;
|
|
- gpio_ib_mode_sel[2] + NET gpio_ib_mode_sel[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 812715 ) N ;
|
|
- gpio_inp_dis[2] + NET gpio_inp_dis[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 778675 ) N ;
|
|
- gpio_oeb[2] + NET gpio_oeb[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 815935 ) N ;
|
|
- gpio_out[2] + NET gpio_out[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 800295 ) N ;
|
|
- gpio_vtrip_sel[2] + NET gpio_vtrip_sel[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 809495 ) N ;
|
|
- gpio_in_h[2] + NET gpio_in_h[2]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 818695 ) N ;
|
|
- gpio_slow_sel[3] + NET gpio_slow_sel[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 980295 ) N ;
|
|
- gpio_in[3] + NET gpio_in[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 971095 ) N ;
|
|
- gpio_dm1[3] + NET gpio_dm1[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 989495 ) N ;
|
|
- gpio_analog_en[3] + NET gpio_analog_en[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 995475 ) N ;
|
|
- gpio_analog_pol[3] + NET gpio_analog_pol[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1001915 ) N ;
|
|
- gpio_analog_sel[3] + NET gpio_analog_sel[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1017095 ) N ;
|
|
- gpio_dm2[3] + NET gpio_dm2[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1020315 ) N ;
|
|
- gpio_dm0[3] + NET gpio_dm0[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 998695 ) N ;
|
|
- gpio_holdover[3] + NET gpio_holdover[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1023535 ) N ;
|
|
- gpio_ib_mode_sel[3] + NET gpio_ib_mode_sel[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1038715 ) N ;
|
|
- gpio_inp_dis[3] + NET gpio_inp_dis[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1004675 ) N ;
|
|
- gpio_oeb[3] + NET gpio_oeb[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1041935 ) N ;
|
|
- gpio_out[3] + NET gpio_out[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1026295 ) N ;
|
|
- gpio_vtrip_sel[3] + NET gpio_vtrip_sel[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1035495 ) N ;
|
|
- gpio_in_h[3] + NET gpio_in_h[3]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1044695 ) N ;
|
|
- gpio_slow_sel[4] + NET gpio_slow_sel[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1205295 ) N ;
|
|
- gpio_in[4] + NET gpio_in[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1196095 ) N ;
|
|
- gpio_dm1[4] + NET gpio_dm1[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1214495 ) N ;
|
|
- gpio_analog_en[4] + NET gpio_analog_en[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1220475 ) N ;
|
|
- gpio_analog_pol[4] + NET gpio_analog_pol[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1226915 ) N ;
|
|
- gpio_analog_sel[4] + NET gpio_analog_sel[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1242095 ) N ;
|
|
- gpio_dm0[4] + NET gpio_dm0[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1223695 ) N ;
|
|
- gpio_dm2[4] + NET gpio_dm2[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1245315 ) N ;
|
|
- gpio_holdover[4] + NET gpio_holdover[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1248535 ) N ;
|
|
- gpio_ib_mode_sel[4] + NET gpio_ib_mode_sel[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1263715 ) N ;
|
|
- gpio_inp_dis[4] + NET gpio_inp_dis[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1229675 ) N ;
|
|
- gpio_oeb[4] + NET gpio_oeb[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1266935 ) N ;
|
|
- gpio_out[4] + NET gpio_out[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1251295 ) N ;
|
|
- gpio_vtrip_sel[4] + NET gpio_vtrip_sel[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1260495 ) N ;
|
|
- gpio_in_h[4] + NET gpio_in_h[4]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1269695 ) N ;
|
|
- gpio_slow_sel[5] + NET gpio_slow_sel[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1430295 ) N ;
|
|
- gpio_in[5] + NET gpio_in[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1421095 ) N ;
|
|
- gpio_dm1[5] + NET gpio_dm1[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1439495 ) N ;
|
|
- gpio_analog_en[5] + NET gpio_analog_en[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1445475 ) N ;
|
|
- gpio_analog_pol[5] + NET gpio_analog_pol[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1451915 ) N ;
|
|
- gpio_analog_sel[5] + NET gpio_analog_sel[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1467095 ) N ;
|
|
- gpio_dm0[5] + NET gpio_dm0[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1448695 ) N ;
|
|
- gpio_dm2[5] + NET gpio_dm2[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1470315 ) N ;
|
|
- gpio_holdover[5] + NET gpio_holdover[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1473535 ) N ;
|
|
- gpio_ib_mode_sel[5] + NET gpio_ib_mode_sel[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1488715 ) N ;
|
|
- gpio_inp_dis[5] + NET gpio_inp_dis[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1454675 ) N ;
|
|
- gpio_oeb[5] + NET gpio_oeb[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1491935 ) N ;
|
|
- gpio_out[5] + NET gpio_out[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1476295 ) N ;
|
|
- gpio_vtrip_sel[5] + NET gpio_vtrip_sel[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1485495 ) N ;
|
|
- gpio_in_h[5] + NET gpio_in_h[5]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1494695 ) N ;
|
|
- gpio_slow_sel[6] + NET gpio_slow_sel[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1656295 ) N ;
|
|
- gpio_in[6] + NET gpio_in[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1647095 ) N ;
|
|
- gpio_dm1[6] + NET gpio_dm1[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1665495 ) N ;
|
|
- gpio_analog_en[6] + NET gpio_analog_en[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1671475 ) N ;
|
|
- gpio_analog_pol[6] + NET gpio_analog_pol[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1677915 ) N ;
|
|
- gpio_analog_sel[6] + NET gpio_analog_sel[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1693095 ) N ;
|
|
- gpio_dm0[6] + NET gpio_dm0[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1674695 ) N ;
|
|
- gpio_dm2[6] + NET gpio_dm2[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1696315 ) N ;
|
|
- gpio_holdover[6] + NET gpio_holdover[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1699535 ) N ;
|
|
- gpio_ib_mode_sel[6] + NET gpio_ib_mode_sel[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1714715 ) N ;
|
|
- gpio_inp_dis[6] + NET gpio_inp_dis[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1680675 ) N ;
|
|
- gpio_oeb[6] + NET gpio_oeb[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1717935 ) N ;
|
|
- gpio_out[6] + NET gpio_out[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1702295 ) N ;
|
|
- gpio_vtrip_sel[6] + NET gpio_vtrip_sel[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1711495 ) N ;
|
|
- gpio_in_h[6] + NET gpio_in_h[6]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 1720695 ) N ;
|
|
- gpio_slow_sel[7] + NET gpio_slow_sel[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2542295 ) N ;
|
|
- gpio_in[7] + NET gpio_in[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2533095 ) N ;
|
|
- gpio_dm1[7] + NET gpio_dm1[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2551495 ) N ;
|
|
- gpio_analog_en[7] + NET gpio_analog_en[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2557475 ) N ;
|
|
- gpio_analog_pol[7] + NET gpio_analog_pol[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2563915 ) N ;
|
|
- gpio_analog_sel[7] + NET gpio_analog_sel[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2579095 ) N ;
|
|
- gpio_dm0[7] + NET gpio_dm0[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2560695 ) N ;
|
|
- gpio_dm2[7] + NET gpio_dm2[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2582315 ) N ;
|
|
- gpio_holdover[7] + NET gpio_holdover[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2585535 ) N ;
|
|
- gpio_ib_mode_sel[7] + NET gpio_ib_mode_sel[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2600715 ) N ;
|
|
- gpio_inp_dis[7] + NET gpio_inp_dis[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2566675 ) N ;
|
|
- gpio_oeb[7] + NET gpio_oeb[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2603935 ) N ;
|
|
- gpio_out[7] + NET gpio_out[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2588295 ) N ;
|
|
- gpio_vtrip_sel[7] + NET gpio_vtrip_sel[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2597495 ) N ;
|
|
- gpio_in_h[7] + NET gpio_in_h[7]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2606695 ) N ;
|
|
- gpio_slow_sel[8] + NET gpio_slow_sel[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2768295 ) N ;
|
|
- gpio_in[8] + NET gpio_in[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2759095 ) N ;
|
|
- gpio_dm1[8] + NET gpio_dm1[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2777495 ) N ;
|
|
- gpio_analog_en[8] + NET gpio_analog_en[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2783475 ) N ;
|
|
- gpio_analog_pol[8] + NET gpio_analog_pol[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2789915 ) N ;
|
|
- gpio_analog_sel[8] + NET gpio_analog_sel[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2805095 ) N ;
|
|
- gpio_dm0[8] + NET gpio_dm0[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2786695 ) N ;
|
|
- gpio_dm2[8] + NET gpio_dm2[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2808315 ) N ;
|
|
- gpio_holdover[8] + NET gpio_holdover[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2811535 ) N ;
|
|
- gpio_ib_mode_sel[8] + NET gpio_ib_mode_sel[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2826715 ) N ;
|
|
- gpio_inp_dis[8] + NET gpio_inp_dis[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2792675 ) N ;
|
|
- gpio_oeb[8] + NET gpio_oeb[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2829935 ) N ;
|
|
- gpio_out[8] + NET gpio_out[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2814295 ) N ;
|
|
- gpio_vtrip_sel[8] + NET gpio_vtrip_sel[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2823495 ) N ;
|
|
- gpio_in_h[8] + NET gpio_in_h[8]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2832695 ) N ;
|
|
- gpio_slow_sel[9] + NET gpio_slow_sel[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2993295 ) N ;
|
|
- gpio_in[9] + NET gpio_in[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 2984095 ) N ;
|
|
- gpio_dm1[9] + NET gpio_dm1[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3002495 ) N ;
|
|
- gpio_analog_en[9] + NET gpio_analog_en[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3008475 ) N ;
|
|
- gpio_analog_pol[9] + NET gpio_analog_pol[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3014915 ) N ;
|
|
- gpio_analog_sel[9] + NET gpio_analog_sel[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3030095 ) N ;
|
|
- gpio_dm0[9] + NET gpio_dm0[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3011695 ) N ;
|
|
- gpio_dm2[9] + NET gpio_dm2[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3033315 ) N ;
|
|
- gpio_holdover[9] + NET gpio_holdover[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3036535 ) N ;
|
|
- gpio_ib_mode_sel[9] + NET gpio_ib_mode_sel[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3051715 ) N ;
|
|
- gpio_inp_dis[9] + NET gpio_inp_dis[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3017675 ) N ;
|
|
- gpio_oeb[9] + NET gpio_oeb[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3054935 ) N ;
|
|
- gpio_out[9] + NET gpio_out[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3039295 ) N ;
|
|
- gpio_vtrip_sel[9] + NET gpio_vtrip_sel[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3048495 ) N ;
|
|
- gpio_in_h[9] + NET gpio_in_h[9]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3057695 ) N ;
|
|
- gpio_slow_sel[10] + NET gpio_slow_sel[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3219295 ) N ;
|
|
- gpio_in[10] + NET gpio_in[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3210095 ) N ;
|
|
- gpio_dm1[10] + NET gpio_dm1[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3228495 ) N ;
|
|
- gpio_analog_en[10] + NET gpio_analog_en[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3234475 ) N ;
|
|
- gpio_analog_pol[10] + NET gpio_analog_pol[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3240915 ) N ;
|
|
- gpio_analog_sel[10] + NET gpio_analog_sel[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3256095 ) N ;
|
|
- gpio_dm0[10] + NET gpio_dm0[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3237695 ) N ;
|
|
- gpio_dm2[10] + NET gpio_dm2[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3259315 ) N ;
|
|
- gpio_holdover[10] + NET gpio_holdover[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3262535 ) N ;
|
|
- gpio_ib_mode_sel[10] + NET gpio_ib_mode_sel[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3277715 ) N ;
|
|
- gpio_inp_dis[10] + NET gpio_inp_dis[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3243675 ) N ;
|
|
- gpio_oeb[10] + NET gpio_oeb[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3280935 ) N ;
|
|
- gpio_out[10] + NET gpio_out[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3265295 ) N ;
|
|
- gpio_vtrip_sel[10] + NET gpio_vtrip_sel[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3274495 ) N ;
|
|
- gpio_in_h[10] + NET gpio_in_h[10]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3283695 ) N ;
|
|
- gpio_slow_sel[11] + NET gpio_slow_sel[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3444295 ) N ;
|
|
- gpio_in[11] + NET gpio_in[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3435095 ) N ;
|
|
- gpio_dm1[11] + NET gpio_dm1[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3453495 ) N ;
|
|
- gpio_holdover[11] + NET gpio_holdover[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3487535 ) N ;
|
|
- gpio_ib_mode_sel[11] + NET gpio_ib_mode_sel[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3502715 ) N ;
|
|
- gpio_inp_dis[11] + NET gpio_inp_dis[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3468675 ) N ;
|
|
- gpio_oeb[11] + NET gpio_oeb[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3505935 ) N ;
|
|
- gpio_out[11] + NET gpio_out[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3490295 ) N ;
|
|
- gpio_vtrip_sel[11] + NET gpio_vtrip_sel[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3499495 ) N ;
|
|
- gpio_analog_en[11] + NET gpio_analog_en[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3459475 ) N ;
|
|
- gpio_analog_pol[11] + NET gpio_analog_pol[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3465915 ) N ;
|
|
- gpio_analog_sel[11] + NET gpio_analog_sel[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3481095 ) N ;
|
|
- gpio_dm0[11] + NET gpio_dm0[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3462695 ) N ;
|
|
- gpio_dm2[11] + NET gpio_dm2[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3484315 ) N ;
|
|
- gpio_in_h[11] + NET gpio_in_h[11]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3508695 ) N ;
|
|
- gpio_slow_sel[12] + NET gpio_slow_sel[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3669295 ) N ;
|
|
- gpio_in[12] + NET gpio_in[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3660095 ) N ;
|
|
- gpio_dm1[12] + NET gpio_dm1[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3678495 ) N ;
|
|
- gpio_analog_en[12] + NET gpio_analog_en[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3684475 ) N ;
|
|
- gpio_analog_pol[12] + NET gpio_analog_pol[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3690915 ) N ;
|
|
- gpio_analog_sel[12] + NET gpio_analog_sel[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3706095 ) N ;
|
|
- gpio_dm0[12] + NET gpio_dm0[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3687695 ) N ;
|
|
- gpio_dm2[12] + NET gpio_dm2[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3709315 ) N ;
|
|
- gpio_holdover[12] + NET gpio_holdover[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3712535 ) N ;
|
|
- gpio_ib_mode_sel[12] + NET gpio_ib_mode_sel[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3727715 ) N ;
|
|
- gpio_inp_dis[12] + NET gpio_inp_dis[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3693675 ) N ;
|
|
- gpio_oeb[12] + NET gpio_oeb[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3730935 ) N ;
|
|
- gpio_out[12] + NET gpio_out[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3715295 ) N ;
|
|
- gpio_vtrip_sel[12] + NET gpio_vtrip_sel[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3724495 ) N ;
|
|
- gpio_in_h[12] + NET gpio_in_h[12]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 3733695 ) N ;
|
|
- gpio_slow_sel[13] + NET gpio_slow_sel[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4115295 ) N ;
|
|
- gpio_in[13] + NET gpio_in[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4106095 ) N ;
|
|
- gpio_dm1[13] + NET gpio_dm1[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4124495 ) N ;
|
|
- gpio_analog_en[13] + NET gpio_analog_en[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4130475 ) N ;
|
|
- gpio_analog_pol[13] + NET gpio_analog_pol[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4136915 ) N ;
|
|
- gpio_analog_sel[13] + NET gpio_analog_sel[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4152095 ) N ;
|
|
- gpio_dm0[13] + NET gpio_dm0[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4133695 ) N ;
|
|
- gpio_dm2[13] + NET gpio_dm2[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4155315 ) N ;
|
|
- gpio_holdover[13] + NET gpio_holdover[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4158535 ) N ;
|
|
- gpio_ib_mode_sel[13] + NET gpio_ib_mode_sel[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4173715 ) N ;
|
|
- gpio_inp_dis[13] + NET gpio_inp_dis[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4139675 ) N ;
|
|
- gpio_oeb[13] + NET gpio_oeb[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4176935 ) N ;
|
|
- gpio_out[13] + NET gpio_out[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4161295 ) N ;
|
|
- gpio_vtrip_sel[13] + NET gpio_vtrip_sel[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4170495 ) N ;
|
|
- gpio_in_h[13] + NET gpio_in_h[13]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4179695 ) N ;
|
|
- gpio_slow_sel[14] + NET gpio_slow_sel[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4561295 ) N ;
|
|
- gpio_in[14] + NET gpio_in[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4552095 ) N ;
|
|
- gpio_dm1[14] + NET gpio_dm1[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4570495 ) N ;
|
|
- gpio_analog_en[14] + NET gpio_analog_en[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4576475 ) N ;
|
|
- gpio_analog_pol[14] + NET gpio_analog_pol[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4582915 ) N ;
|
|
- gpio_analog_sel[14] + NET gpio_analog_sel[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4598095 ) N ;
|
|
- gpio_dm0[14] + NET gpio_dm0[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4579695 ) N ;
|
|
- gpio_dm2[14] + NET gpio_dm2[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4601315 ) N ;
|
|
- gpio_holdover[14] + NET gpio_holdover[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4604535 ) N ;
|
|
- gpio_ib_mode_sel[14] + NET gpio_ib_mode_sel[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4619715 ) N ;
|
|
- gpio_inp_dis[14] + NET gpio_inp_dis[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4585675 ) N ;
|
|
- gpio_oeb[14] + NET gpio_oeb[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4622935 ) N ;
|
|
- gpio_out[14] + NET gpio_out[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4607295 ) N ;
|
|
- gpio_vtrip_sel[14] + NET gpio_vtrip_sel[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4616495 ) N ;
|
|
- gpio_in_h[14] + NET gpio_in_h[14]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( 3167480 4625695 ) N ;
|
|
- gpio_in[24] + NET gpio_in[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4635535 ) N ;
|
|
- gpio_slow_sel[24] + NET gpio_slow_sel[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4626335 ) N ;
|
|
- gpio_dm1[24] + NET gpio_dm1[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4617135 ) N ;
|
|
- gpio_analog_en[24] + NET gpio_analog_en[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4611155 ) N ;
|
|
- gpio_dm0[24] + NET gpio_dm0[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4607935 ) N ;
|
|
- gpio_analog_pol[24] + NET gpio_analog_pol[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4604715 ) N ;
|
|
- gpio_inp_dis[24] + NET gpio_inp_dis[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4601955 ) N ;
|
|
- gpio_analog_sel[24] + NET gpio_analog_sel[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4589535 ) N ;
|
|
- gpio_dm2[24] + NET gpio_dm2[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4586315 ) N ;
|
|
- gpio_holdover[24] + NET gpio_holdover[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4583095 ) N ;
|
|
- gpio_out[24] + NET gpio_out[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4580335 ) N ;
|
|
- gpio_vtrip_sel[24] + NET gpio_vtrip_sel[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4571135 ) N ;
|
|
- gpio_ib_mode_sel[24] + NET gpio_ib_mode_sel[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4567915 ) N ;
|
|
- gpio_oeb[24] + NET gpio_oeb[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4564695 ) N ;
|
|
- gpio_in_h[24] + NET gpio_in_h[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -175 ) ( 1150 175 ) + PLACED ( -850 4561935 ) N ;
|
|
- analog_io[24] + NET analog_io[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -320 ) ( 1150 320 ) + PLACED ( -850 4623120 ) N ;
|
|
- analog_noesd_io[24] + NET analog_noesd_io[24]
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -535 ) ( 1150 535 ) + PLACED ( -850 4613920 ) N ;
|
|
- gpio_loopback_zero[23] + NET gpio_loopback_zero[23]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 137640 4767490 ) N ;
|
|
- gpio_loopback_zero[22] + NET gpio_loopback_zero[22]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 393640 4767490 ) N ;
|
|
- gpio_loopback_zero[21] + NET gpio_loopback_zero[21]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 649640 4767490 ) N ;
|
|
- gpio_loopback_zero[20] + NET gpio_loopback_zero[20]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 905640 4767490 ) N ;
|
|
- gpio_loopback_zero[19] + NET gpio_loopback_zero[19]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 1161640 4767490 ) N ;
|
|
- gpio_loopback_zero[18] + NET gpio_loopback_zero[18]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 1683640 4767490 ) N ;
|
|
- gpio_loopback_zero[17] + NET gpio_loopback_zero[17]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2128640 4767490 ) N ;
|
|
- gpio_loopback_zero[16] + NET gpio_loopback_zero[16]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2384640 4767490 ) N ;
|
|
- gpio_loopback_zero[15] + NET gpio_loopback_zero[15]
|
|
+ PORT
|
|
+ LAYER met2 ( -150 -1140 ) ( 150 1140 ) + PLACED ( 2881640 4767490 ) N ;
|
|
- vccd1 + NET vccd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -12000 ) ( 1150 12000 ) + PLACED ( 3167480 4389810 ) N ;
|
|
- vssd1 + NET vssd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11655 ) ( 1150 11655 ) + PLACED ( 3167480 4364705 ) N ;
|
|
- vccd1 + NET vccd1
|
|
+ PORT
|
|
+ LAYER met3 ( -1150 -11975 ) ( 1150 11975 ) + PLACED ( 3167480 4339585 ) N ;
|
|
END PINS
|
|
|
|
END DESIGN
|
|
|