mirror of https://github.com/efabless/caravel.git
534 lines
20 KiB
Python
Executable File
534 lines
20 KiB
Python
Executable File
#!/usr/bin/env python3
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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#----------------------------------------------------------------------
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#
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# gen_gpio_defaults.py ---
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#
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# Manipulate the magic database to create and apply defaults to
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# the GPIO control blocks based on the user's specification in the
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# user_defines.v file.
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#
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# The GPIO defaults block contains 13 bits that set the state of the
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# GPIO on power-up. GPIOs 0 to 4 in the user project area are fixed
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# and cannot be modified (to maintain access to the housekeeping SPI
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# on startup). GPIOs 5 to 37 are by default set to be an input pad
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# controlled by the user project. The file "user_defines.v" contains
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# the state specified by the user for each GPIO pad, and is what is
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# used in verilog simulation.
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#
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# This script parses the user_defines.v file to determine the state
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# of each GPIO. Then it creates as many new layouts as needed to
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# represent all unique states, modifies the caravel.mag layout
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# to replace the default layouts with the new ones as needed, and
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# generates GDS files for each of the layouts.
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#
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# gpio_defaults_block layout map:
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# Positions marked (in microns) for value = 0. For value = 1, move
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# the via 0.92um to the right. The given position is the lower left
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# corner position of the via. The via itself is 0.17um x 0.17um.
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# The values below are for the file gpio_defaults_block_1403.
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# Positions marked "Y" for "Programmed One?" are already moved to
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# the left, and so should be move 0.69um to the right if the bit
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# should be zero.
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#
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# Signal Via position (um)
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# name X Y
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#-------------------------------------------------------------------
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# gpio_defaults[0] 7.505 17.425
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# gpio_defaults[1] 11.645 17.425
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# gpio_defaults[2] 4.745 6.545
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# gpio_defaults[3] 7.965 6.545
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# gpio_defaults[4] 11.645 6.545
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# gpio_defaults[5] 5.205 9.605
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# gpio_defaults[6] 5.205 11.985
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# gpio_defaults[7] 8.425 15.045
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# gpio_defaults[8] 7.965 20.485
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# gpio_defaults[9] 4.745 20.485
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# gpio_defaults[10] 5.205 15.045
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# gpio_defaults[11] 12.105 9.605
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# gpio_defaults[12] 8.885 9.605
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#-------------------------------------------------------------------
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import os
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import sys
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import re
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import glob
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import subprocess
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import gzip
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def usage():
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print('Usage:')
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print('gen_gpio_defaults.py [<path_to_project>] [-test]')
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print('')
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print('where:')
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print(' <path_to_project> is the path to the project top level directory.')
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print('')
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print(' If <path_to_project> is not given, then it is assumed to be the cwd.')
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print(' The file "user_defines.v" must exist in verilog/rtl/ relative to')
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print(' <path_to_project>.')
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return 0
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def smart_open(filename, mode="rt"):
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"""
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Opens a file normally if uncompressed, or with gzip if it’s a .gz file.
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Args:
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filename (str): Path to the file.
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mode (str): File mode ('rt' for text, 'rb' for binary, etc.).
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Returns:
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File object (either normal open or gzip open).
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"""
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if filename.endswith(".gz"):
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return gzip.open(filename, mode)
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else:
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return open(filename, mode)
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if __name__ == '__main__':
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# Coordinate pairs in microns for the zero position on each bit
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via_pos = [[7.505, 17.425], [11.645, 17.425], [4.745, 6.545], [7.965, 6.545],
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[11.645, 6.545], [5.205, 9.605], [5.205, 11.985], [8.425, 15.045],
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[7.965, 20.485], [4.745, 20.485], [5.205, 15.045], [12.105, 9.605],
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[8.885, 9.605]]
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optionlist = []
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arguments = []
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debugmode = False
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testmode = False
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for option in sys.argv[1:]:
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if option.find('-', 0) == 0:
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optionlist.append(option)
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else:
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arguments.append(option)
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if len(arguments) > 2:
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print("Wrong number of arguments given to gen_gpio_defaults.py.")
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usage()
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sys.exit(0)
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if '-debug' in optionlist:
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debugmode = True
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if '-test' in optionlist:
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testmode = True
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user_project_path = None
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if len(arguments) == 0:
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user_project_path = os.getcwd()
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else:
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user_project_path = arguments[0]
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if not os.path.isdir(user_project_path):
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print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
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sys.exit(1)
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magpath = user_project_path + '/mag'
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vpath = user_project_path + '/verilog'
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glpath = vpath + '/gl'
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try:
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caravel_path = os.environ['CARAVEL_ROOT']
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except:
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print('Warning: CARAVEL_ROOT not set; assuming the cwd.')
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caravel_path = os.getcwd()
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# Check paths
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if not os.path.isdir(vpath):
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print('No directory ' + vpath + ' found (path to verilog).')
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sys.exit(1)
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if not os.path.isdir(glpath):
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print('No directory ' + glpath + ' found (path to gate-level verilog).')
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sys.exit(1)
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if not os.path.isdir(magpath):
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print('No directory ' + magpath + ' found (path to magic databases).')
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sys.exit(1)
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# Parse the user defines verilog file
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kvpairs = {}
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user_defines_path = vpath + '/rtl/user_defines.v'
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if not os.path.isfile(user_defines_path):
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user_defines_path = caravel_path + '/verilog/rtl/user_defines.v'
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if os.path.isfile(user_defines_path):
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with open(user_defines_path, 'r') as ifile:
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raw_data = ifile.read()
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comment_pattern = r'//.*|/\*[\s\S]*?\*/'
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data_without_comments = re.sub(comment_pattern, '', raw_data)
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for line in data_without_comments.splitlines():
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tokens = line.split()
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if len(tokens) >= 3:
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if tokens[0] == '`define':
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if tokens[2][0] == '`':
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# If definition is nested, substitute value.
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try:
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tokens[2] = kvpairs[tokens[2]]
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except:
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print('Error: Used unknown definition ' + tokens[2])
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kvpairs['`' + tokens[1]] = tokens[2]
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else:
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print('Error: No user_defines.v file found.')
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sys.exit(1)
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# Set additional dictionary entries for the fixed-configuration
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# GPIOs 0 to 4. This allows the layout to have the default
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# gpio_defaults_block layout, and this script will change it as
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# needed.
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kvpairs["`USER_CONFIG_GPIO_0_INIT"] = "13'h1803"
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kvpairs["`USER_CONFIG_GPIO_1_INIT"] = "13'h1803"
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kvpairs["`USER_CONFIG_GPIO_2_INIT"] = "13'h0403"
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kvpairs["`USER_CONFIG_GPIO_3_INIT"] = "13'h0801"
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kvpairs["`USER_CONFIG_GPIO_4_INIT"] = "13'h0403"
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# Generate zero and one coordinates for each via
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llx_zero = []
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lly_zero = []
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urx_zero = []
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ury_zero = []
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llx_one = []
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lly_one = []
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urx_one = []
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ury_one = []
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zero_string = []
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one_string = []
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for i in range(0, 13):
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llx_zero = round(via_pos[i][0] * 200)
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lly_zero = round(via_pos[i][1] * 200)
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urx_zero = llx_zero + 34
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ury_zero = lly_zero + 34
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llx_one = llx_zero + 184
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lly_one = lly_zero
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urx_one = urx_zero + 184
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ury_one = ury_zero
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zero_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_zero, lly_zero, urx_zero, ury_zero))
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one_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_one, lly_one, urx_one, ury_one))
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# Create new cells for each unique type
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print('Step 1: Create new cells for new GPIO default vectors.')
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cellsused = [None] * 38
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# Remove pre-existing versions of mag and verilog files because they may be out-of-date.
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for old_mag_file in glob.glob(magpath + '/gpio_defaults_block_*.mag'):
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os.remove(old_mag_file)
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for old_verilog_file in glob.glob(glpath + '/gpio_defaults_block_*.v'):
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os.remove(old_verilog_file)
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for i in range(0, 38):
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config_name = '`USER_CONFIG_GPIO_' + str(i) + '_INIT'
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try:
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config_value = kvpairs[config_name]
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except:
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print('No configuration specified for GPIO ' + str(i) + '; skipping.')
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continue
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valid_value = r"^13'h[0-9a-fA-F]{4}$"
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value_match = re.match(valid_value, config_value)
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if not value_match:
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print('Error: Default value ' + config_value + ' is not a 4-digit hex number; skipping')
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continue
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try:
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default_str = config_value[-4:]
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binval = '{:013b}'.format(int(default_str, 16))
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if len(binval) > 13:
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print('Error: Default value ' + config_value + ' is not a 4-digit hex number; skipping')
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continue
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except:
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print('Error: Default value ' + config_value + ' is not a 4-digit hex number; skipping')
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continue
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cell_name = 'gpio_defaults_block_' + default_str.lower()
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mag_file = magpath + '/' + cell_name + '.mag'
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cellsused[i] = cell_name
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# Record which bits need to be set for this binval
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bitflips = []
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notflipped = []
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for j in range(0, 13):
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if binval[12 - j] == '1':
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bitflips.append(j)
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else:
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notflipped.append(j)
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if not os.path.isfile(mag_file):
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# A cell with this set of defaults doesn't exist, so make it
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# First read the 0000 cell, then write to mag_path while
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# changing the position of vias on the "1" bits
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with open(caravel_path + '/mag/gpio_defaults_block.mag', 'r') as ifile:
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maglines = ifile.read().splitlines()
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outlines = []
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for magline in maglines:
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is_flipped = False
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reverse_flipped = False
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for bitflip in bitflips:
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if magline == zero_string[bitflip]:
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is_flipped = True
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break
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if not is_flipped:
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for bitflip in notflipped:
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if magline == one_string[bitflip]:
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reverse_flipped = True
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break
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if is_flipped:
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outlines.append(one_string[bitflip])
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elif reverse_flipped:
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outlines.append(zero_string[bitflip])
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else:
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outlines.append(magline)
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print('Creating new layout file ' + mag_file)
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if testmode:
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print('(Test only)')
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else:
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with open(mag_file, 'w') as ofile:
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for outline in outlines:
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print(outline, file=ofile)
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else:
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print('Layout file ' + mag_file + ' already exists and does not need to be generated.')
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gl_file = glpath + '/' + cell_name + '.v'
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defrex = re.compile('[ \t]*assign[ \t]+gpio_defaults\[([0-9]+)\]')
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if not os.path.isfile(gl_file):
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# A cell with this set of defaults doesn't exist, so make it
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# First read the default cell, then write to gl_path while
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# changing the assignment statements at the bottom of each file.
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with open(caravel_path + '/verilog/gl/gpio_defaults_block.v', 'r') as ifile:
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vlines = ifile.read().splitlines()
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outlines = []
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for vline in vlines:
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is_flipped = False
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is_reversed = False
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dmatch = defrex.match(vline)
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if dmatch:
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bitidx = int(dmatch.group(1))
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if bitidx in bitflips:
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is_flipped = True
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else:
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is_reversed = True
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if is_flipped:
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outlines.append(re.sub('_low', '_high', vline))
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elif is_reversed:
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outlines.append(re.sub('_high', '_low', vline))
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elif 'gpio_defaults_block' in vline:
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outlines.append(re.sub('gpio_defaults_block', cell_name, vline))
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else:
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outlines.append(vline)
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print('Creating new gate-level verilog file ' + gl_file)
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if testmode:
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print('(Test only)')
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else:
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with open(gl_file, 'w') as ofile:
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for outline in outlines:
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print(outline, file=ofile)
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else:
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print('Gate-level verilog file ' + gl_file + ' already exists and does not need to be generated.')
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print('Step 2: Modify top-level layouts to use the specified defaults.')
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# Create a backup of the caravan and caravel layouts
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# if not testmode:
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# shutil.copy(magpath + '/caravel.mag', magpath + '/caravel.mag.bak')
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# shutil.copy(magpath + '/caravan.mag', magpath + '/caravan.mag.bak')
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idx1rex = re.compile('gpio_defaults_block_([0-9]+)..([0-9]+)')
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idx2rex = re.compile('gpio_defaults_block_([0-9]+)')
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if testmode:
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print('Test only: Caravel core layout:')
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# Check for compressed layout
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if os.path.isfile(caravel_path + '/mag/caravel_core.mag'):
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caravel_core_magfile = caravel_path + '/mag/caravel_core.mag'
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elif os.path.isfile(caravel_path + '/mag/caravel_core.mag.gz'):
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caravel_core_magfile = caravel_path + '/mag/caravel_core.mag.gz'
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else:
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print(f' Could not find {caravel_path}/mag/caravel_core.mag[.gz]')
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sys.exit(2)
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with smart_open(caravel_core_magfile, 'rt') as ifile:
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maglines = ifile.read().splitlines()
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outlines = []
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for magline in maglines:
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if magline.startswith('use '):
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tokens = magline.split()
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instname = tokens[2]
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if instname.startswith('gpio_defaults_block_'):
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imatch = idx1rex.match(instname)
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if imatch:
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gpioidx = int(imatch.group(1)) + int(imatch.group(2))
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else:
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imatch = idx2rex.match(instname)
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if imatch:
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gpioidx = int(imatch.group(1))
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else:
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print('Error: instance ' + instname + ' not a defaults block?')
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cellname = cellsused[gpioidx]
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if cellname:
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tokens[1] = cellname
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outlines.append(' '.join(tokens))
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if testmode:
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print('Replacing line: ' + magline)
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print('With: ' + ' '.join(tokens))
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else:
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outlines.append(magline)
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else:
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outlines.append(magline)
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if not testmode:
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with open(magpath + '/caravel_core.mag', 'w') as ofile:
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for outline in outlines:
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print(outline, file=ofile)
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# Do the same to the core gate-level verilog
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inst1rex = re.compile('[ \t]*(gpio_defaults_block_?[0-1]?[0-9A-Fa-f]*)[ \t]+.?gpio_defaults_block_([0-9]+).([0-9]+)')
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inst2rex = re.compile('[ \t]*(gpio_defaults_block_?[0-1]?[0-9A-Fa-f]*)[ \t]+gpio_defaults_block_([0-9]+)')
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if testmode:
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print('Test only: Caravel top gate-level verilog:')
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with open(caravel_path + '/verilog/gl/caravel_core.v', 'r') as ifile:
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vlines = ifile.read().splitlines()
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outlines = []
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for vline in vlines:
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imatch = inst1rex.match(vline)
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if imatch:
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gpioidx = int(imatch.group(2)) + int(imatch.group(3))
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else:
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imatch = inst2rex.match(vline)
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if imatch:
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gpioidx = int(imatch.group(2))
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if imatch:
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gpioname = imatch.group(1)
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cellname = cellsused[gpioidx]
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if cellname:
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outlines.append(re.sub(gpioname, cellname, vline, 1))
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if testmode:
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print('Replacing line: ' + vline)
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print('With: ' + outlines[-1])
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else:
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outlines.append(vline)
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else:
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outlines.append(vline)
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if not testmode:
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with open(glpath + '/caravel_core.v', 'w') as ofile:
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for outline in outlines:
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print(outline, file=ofile)
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# IMPORTANT NOTE:
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# This needs to be changed to caravan_core, but the cell does not yet
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# exist.
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if testmode:
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print('Test only: Caravan layout:')
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# Check for compressed layout
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if os.path.isfile(caravel_path + '/mag/caravan_core.mag'):
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caravan_core_magfile = caravel_path + '/mag/caravan_core.mag'
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elif os.path.isfile(caravel_path + '/mag/caravan_core.mag.gz'):
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caravan_core_magfile = caravel_path + '/mag/caravan_core.mag.gz'
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else:
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print(f' Could not find {caravel_path}/mag/caravan_core.mag[.gz]')
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sys.exit(2)
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with smart_open(caravan_core_magfile, 'rt') as ifile:
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maglines = ifile.read().splitlines()
|
||
outlines = []
|
||
for magline in maglines:
|
||
if magline.startswith('use '):
|
||
tokens = magline.split()
|
||
instname = tokens[2]
|
||
if instname.startswith('gpio_defaults_block_'):
|
||
imatch = idx1rex.match(instname)
|
||
if imatch:
|
||
gpioidx = int(imatch.group(1)) + int(imatch.group(2))
|
||
else:
|
||
imatch = idx2rex.match(instname)
|
||
if imatch:
|
||
gpioidx = int(imatch.group(1))
|
||
else:
|
||
print('Error: instance ' + instname + ' not a defaults block?')
|
||
cellname = cellsused[gpioidx]
|
||
if cellname:
|
||
tokens[1] = cellname
|
||
outlines.append(' '.join(tokens))
|
||
if testmode:
|
||
print('Replacing line: ' + magline)
|
||
print('With: ' + ' '.join(tokens))
|
||
else:
|
||
outlines.append(magline)
|
||
else:
|
||
outlines.append(magline)
|
||
|
||
if not testmode:
|
||
with open(magpath + '/caravan_core.mag', 'w') as ofile:
|
||
for outline in outlines:
|
||
print(outline, file=ofile)
|
||
|
||
# Do the same to the top gate-level verilog
|
||
|
||
if testmode:
|
||
print('Test only: Caravan top gate-level verilog:')
|
||
with open(caravel_path + '/verilog/gl/caravan_core.v', 'r') as ifile:
|
||
vlines = ifile.read().splitlines()
|
||
outlines = []
|
||
for vline in vlines:
|
||
imatch = inst1rex.match(vline)
|
||
if imatch:
|
||
gpioidx = int(imatch.group(2)) + int(imatch.group(3))
|
||
else:
|
||
imatch = inst2rex.match(vline)
|
||
if imatch:
|
||
gpioidx = int(imatch.group(2))
|
||
if imatch:
|
||
gpioname = imatch.group(1)
|
||
cellname = cellsused[gpioidx]
|
||
if cellname:
|
||
outlines.append(re.sub(gpioname, cellname, vline, 1))
|
||
if testmode:
|
||
print('Replacing line: ' + vline)
|
||
print('With: ' + outlines[-1])
|
||
else:
|
||
outlines.append(vline)
|
||
else:
|
||
outlines.append(vline)
|
||
|
||
if not testmode:
|
||
with open(glpath + '/caravan_core.v', 'w') as ofile:
|
||
for outline in outlines:
|
||
print(outline, file=ofile)
|
||
|
||
print('Done.')
|
||
sys.exit(0)
|