Max transition on internal signals: 1.25ns
Hold WNS (F2F): 0.00
Setup WNS (F2F): 0.00

lvs clean: Y
drc clean: Y
cvc clean: N/A - cvc doesn't work with designs that have macros(gpio_logic_high) 
Antenna Violations: 0
Antenna Violations (400-500): 0
Antenna Violations (500-800): 0
Antenna Violations (800-1000): 0

non-physical cells: 264 - 131 = 133
decap cell count: 42
% decap: 42 / 264  * 100 = 15.9%
max ir drop: 1.01e-09 V 

Verilog "assign" in the netlist: N
Does the netlist show cells from different libraries: N
Does the macro have mixed power domains powered cells: Y - gpio_logic_high uses another power domain
Any internal macros with floating input ports: N
Output ports not connected to any logic inside the macro: N
Input ports not connected to any logic inside the macro: N
Tri-state cells are connected directly to output ports: N
Analog Signals are not digitally buffered: N
Output ports are properly buffred (>=buf_4): Y
buffer cells count: 56
logic cells that are not buffers count: 133 - 56 = 77
buf_1 & buf_2 cells count: 29
0.5mm or longer wire count: 0