Metric,Value
timing__setup__ws__corner:nom_tt_025C_1v80,1.624232
timing__hold__ws__corner:nom_tt_025C_1v80,0.274621
design__instance__area,3221.84
design__instance__count,520
design__instance__total_power,1.3465
design__die__bbox,0.0 0.0 100.0 75.0
design__core__bbox,5.52 5.44 94.3 68.0
design__io,39
design__die__area,7500
design__core__area,5554.08
design__instance__count__stdcell,520
design__instance__area__stdcell,3221.84
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.580086
design__instance__utilization__stdcell,0.580086
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,6909.71
design__violations,0
antenna__violating__nets,0
antenna__violating__pins,0
antenna__count,0
route__net,394
route__net__special,2
route__drc_errors__iter:1,168
route__wirelength__iter:1,7682
route__drc_errors__iter:2,55
route__wirelength__iter:2,7648
route__drc_errors__iter:3,123
route__wirelength__iter:3,7652
route__drc_errors__iter:4,1
route__wirelength__iter:4,7689
route__drc_errors__iter:5,0
route__wirelength__iter:5,7689
route__drc_errors,0
route__wirelength,7689
route__vias,2382
route__vias__singlecut,2382
route__vias__multicut,0
design__disconnected_pins__count,0
route__wirelength__max,252.91
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.0006281010573729873
power__switching__total,0.0010574385523796082
power__leakage__total,3.840616269457087e-09
power__total,0.0016855434514582157
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.026419
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.026648
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.026351
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.026574
timing__hold__ws__corner:nom_ss_100C_1v60,0.67865
timing__setup__ws__corner:nom_ss_100C_1v60,-2.045736
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,-9.303928
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
timing__setup__wns__corner:nom_ss_100C_1v60,-2.045736
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_vio__count__corner:nom_ss_100C_1v60,8
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,7
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.026447
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.026678
timing__hold__ws__corner:nom_ff_n40C_1v95,0.139551
timing__setup__ws__corner:nom_ff_n40C_1v95,2.729408
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,2
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.019092
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.019238
timing__hold__ws__corner:min_tt_025C_1v80,0.274164
timing__setup__ws__corner:min_tt_025C_1v80,1.663321
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0.0
timing__setup__wns__corner:min_tt_025C_1v80,0.0
timing__hold_vio__count__corner:min_tt_025C_1v80,0
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,2
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.018972
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.019113
timing__hold__ws__corner:min_ss_100C_1v60,0.67585
timing__setup__ws__corner:min_ss_100C_1v60,-1.833309
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,-8.749656
timing__hold__wns__corner:min_ss_100C_1v60,0.0
timing__setup__wns__corner:min_ss_100C_1v60,-1.833309
timing__hold_vio__count__corner:min_ss_100C_1v60,0
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,8
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,7
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.01919
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.019339
timing__hold__ws__corner:min_ff_n40C_1v95,0.139087
timing__setup__ws__corner:min_ff_n40C_1v95,2.757252
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,2
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.04563
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.04611
timing__hold__ws__corner:max_tt_025C_1v80,0.273634
timing__setup__ws__corner:max_tt_025C_1v80,1.585729
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0.0
timing__setup__wns__corner:max_tt_025C_1v80,0.0
timing__hold_vio__count__corner:max_tt_025C_1v80,0
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,2
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.046207
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.046689
timing__hold__ws__corner:max_ss_100C_1v60,0.680917
timing__setup__ws__corner:max_ss_100C_1v60,-2.245377
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,-9.948954
timing__hold__wns__corner:max_ss_100C_1v60,0.0
timing__setup__wns__corner:max_ss_100C_1v60,-2.245377
timing__hold_vio__count__corner:max_ss_100C_1v60,0
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,8
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,7
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.044996
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.045482
timing__hold__ws__corner:max_ff_n40C_1v95,0.139449
timing__setup__ws__corner:max_ff_n40C_1v95,2.701741
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
design__max_slew_violation__count,0
design__max_fanout_violation__count,18
design__max_cap_violation__count,0
clock__skew__worst_hold,-0.018972
clock__skew__worst_setup,0.046689
timing__hold__ws,0.139087
timing__setup__ws,-2.245377
timing__hold__tns,0.0
timing__setup__tns,-28.002538
timing__hold__wns,0.0
timing__setup__wns,-2.245377
timing__hold_vio__count,0
timing__hold_r2r_vio__count,0
timing__setup_vio__count,24
timing__setup_r2r_vio__count,21
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,0.000890999999999999973444853029747036998742260038852691650390625
ir__drop__worst,0.00120999999999999992110477631257481334614567458629608154296875
design__xor_difference__count,0
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
design__lvs_net_differences__count,0
design__lvs_property_fails__count,0
design__lvs_errors__count,0
design__lvs_unmatched_devices__count,0
design__lvs_unmatched_nets__count,0
design__lvs_unmatched_pins__count,0