############################################################################### # Created by write_sdc # Mon Oct 3 15:38:06 2022 ############################################################################### current_design mgmt_protect ############################################################################### # Timing Constraints ############################################################################### create_clock -name v_clk -period 4 set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_clk2}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {caravel_rstn}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[100]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[101]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[102]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[103]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[104]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[105]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[106]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[107]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[108]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[109]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[110]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[111]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[112]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[113]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[114]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[115]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[116]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[117]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[118]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[119]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[120]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[121]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[122]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[123]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[124]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[125]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[126]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[127]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[32]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[33]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[34]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[35]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[36]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[37]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[38]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[39]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[40]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[41]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[42]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[43]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[44]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[45]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[46]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[47]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[48]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[49]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[50]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[51]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[52]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[53]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[54]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[55]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[56]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[57]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[58]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[59]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[60]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[61]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[62]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[63]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[64]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[65]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[66]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[67]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[68]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[69]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[70]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[71]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[72]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[73]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[74]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[75]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[76]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[77]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[78]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[79]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[80]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[81]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[82]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[83]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[84]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[85]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[86]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[87]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[88]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[89]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[90]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[91]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[92]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[93]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[94]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[95]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[96]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[97]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[98]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[99]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_core[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[100]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[101]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[102]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[103]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[104]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[105]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[106]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[107]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[108]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[109]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[110]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[111]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[112]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[113]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[114]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[115]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[116]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[117]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[118]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[119]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[120]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[121]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[122]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[123]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[124]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[125]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[126]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[127]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[32]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[33]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[34]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[35]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[36]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[37]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[38]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[39]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[40]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[41]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[42]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[43]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[44]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[45]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[46]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[47]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[48]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[49]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[50]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[51]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[52]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[53]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[54]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[55]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[56]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[57]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[58]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[59]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[60]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[61]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[62]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[63]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[64]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[65]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[66]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[67]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[68]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[69]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[70]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[71]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[72]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[73]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[74]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[75]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[76]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[77]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[78]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[79]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[80]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[81]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[82]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[83]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[84]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[85]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[86]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[87]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[88]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[89]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[90]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[91]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[92]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[93]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[94]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[95]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[96]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[97]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[98]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[99]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_out_mprj[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[100]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[101]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[102]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[103]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[104]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[105]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[106]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[107]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[108]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[109]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[110]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[111]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[112]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[113]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[114]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[115]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[116]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[117]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[118]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[119]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[120]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[121]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[122]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[123]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[124]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[125]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[126]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[127]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[32]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[33]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[34]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[35]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[36]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[37]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[38]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[39]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[40]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[41]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[42]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[43]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[44]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[45]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[46]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[47]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[48]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[49]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[50]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[51]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[52]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[53]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[54]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[55]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[56]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[57]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[58]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[59]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[60]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[61]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[62]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[63]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[64]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[65]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[66]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[67]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[68]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[69]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[70]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[71]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[72]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[73]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[74]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[75]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[76]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[77]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[78]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[79]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[80]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[81]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[82]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[83]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[84]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[85]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[86]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[87]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[88]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[89]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[90]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[91]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[92]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[93]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[94]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[95]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[96]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[97]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[98]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[99]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_iena_mprj[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[100]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[101]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[102]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[103]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[104]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[105]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[106]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[107]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[108]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[109]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[110]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[111]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[112]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[113]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[114]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[115]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[116]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[117]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[118]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[119]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[120]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[121]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[122]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[123]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[124]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[125]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[126]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[127]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[32]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[33]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[34]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[35]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[36]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[37]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[38]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[39]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[40]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[41]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[42]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[43]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[44]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[45]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[46]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[47]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[48]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[49]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[50]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[51]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[52]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[53]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[54]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[55]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[56]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[57]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[58]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[59]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[60]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[61]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[62]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[63]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[64]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[65]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[66]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[67]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[68]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[69]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[70]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[71]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[72]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[73]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[74]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[75]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[76]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[77]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[78]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[79]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[80]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[81]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[82]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[83]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[84]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[85]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[86]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[87]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[88]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[89]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[90]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[91]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[92]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[93]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[94]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[95]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[96]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[97]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[98]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[99]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_mprj[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_ack_i_user}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_core[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_cyc_o_core}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_user[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[10]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[11]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[12]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[13]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[14]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[15]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[16]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[17]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[18]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[19]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[20]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[21]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[22]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[23]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[24]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[25]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[26]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[27]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[28]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[29]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[30]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[31]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[4]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[5]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[6]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[7]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[8]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_core[9]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_iena_wb}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_core[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_core[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_core[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_core[3]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_stb_o_core}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_we_o_core}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_core[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_core[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_core[2]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_ena[0]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_ena[1]}] set_input_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq_ena[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[100]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[101]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[102]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[103]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[104]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[105]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[106]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[107]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[108]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[109]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[110]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[111]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[112]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[113]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[114]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[115]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[116]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[117]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[118]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[119]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[120]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[121]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[122]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[123]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[124]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[125]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[126]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[127]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[32]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[33]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[34]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[35]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[36]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[37]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[38]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[39]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[40]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[41]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[42]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[43]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[44]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[45]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[46]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[47]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[48]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[49]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[50]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[51]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[52]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[53]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[54]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[55]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[56]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[57]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[58]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[59]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[60]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[61]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[62]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[63]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[64]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[65]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[66]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[67]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[68]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[69]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[70]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[71]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[72]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[73]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[74]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[75]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[76]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[77]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[78]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[79]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[80]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[81]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[82]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[83]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[84]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[85]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[86]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[87]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[88]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[89]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[90]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[91]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[92]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[93]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[94]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[95]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[96]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[97]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[98]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[99]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_core[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[100]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[101]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[102]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[103]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[104]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[105]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[106]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[107]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[108]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[109]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[110]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[111]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[112]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[113]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[114]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[115]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[116]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[117]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[118]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[119]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[120]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[121]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[122]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[123]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[124]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[125]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[126]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[127]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[32]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[33]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[34]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[35]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[36]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[37]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[38]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[39]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[40]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[41]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[42]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[43]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[44]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[45]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[46]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[47]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[48]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[49]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[50]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[51]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[52]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[53]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[54]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[55]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[56]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[57]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[58]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[59]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[60]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[61]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[62]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[63]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[64]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[65]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[66]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[67]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[68]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[69]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[70]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[71]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[72]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[73]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[74]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[75]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[76]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[77]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[78]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[79]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[80]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[81]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[82]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[83]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[84]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[85]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[86]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[87]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[88]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[89]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[90]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[91]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[92]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[93]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[94]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[95]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[96]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[97]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[98]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[99]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_data_in_mprj[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[100]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[101]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[102]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[103]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[104]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[105]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[106]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[107]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[108]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[109]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[110]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[111]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[112]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[113]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[114]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[115]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[116]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[117]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[118]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[119]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[120]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[121]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[122]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[123]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[124]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[125]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[126]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[127]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[32]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[33]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[34]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[35]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[36]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[37]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[38]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[39]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[40]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[41]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[42]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[43]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[44]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[45]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[46]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[47]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[48]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[49]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[50]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[51]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[52]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[53]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[54]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[55]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[56]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[57]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[58]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[59]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[60]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[61]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[62]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[63]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[64]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[65]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[66]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[67]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[68]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[69]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[70]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[71]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[72]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[73]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[74]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[75]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[76]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[77]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[78]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[79]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[80]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[81]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[82]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[83]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[84]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[85]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[86]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[87]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[88]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[89]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[90]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[91]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[92]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[93]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[94]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[95]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[96]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[97]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[98]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[99]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {la_oenb_core[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_ack_i_core}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_adr_o_user[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_cyc_o_user}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_i_core[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[10]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[11]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[12]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[13]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[14]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[15]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[16]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[17]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[18]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[19]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[20]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[21]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[22]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[23]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[24]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[25]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[26]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[27]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[28]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[29]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[30]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[31]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[4]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[5]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[6]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[7]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[8]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_dat_o_user[9]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_user[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_user[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_user[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_sel_o_user[3]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_stb_o_user}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {mprj_we_o_user}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user1_vcc_powergood}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user1_vdd_powergood}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user2_vcc_powergood}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user2_vdd_powergood}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_clock}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_clock2}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq[0]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq[1]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_irq[2]}] set_output_delay 1.0000 -clock [get_clocks {v_clk}] -add_delay [get_ports {user_reset}] ############################################################################### # Environment ############################################################################### set_load -pin_load 0.2000 [get_ports {mprj_ack_i_core}] set_load -pin_load 0.2000 [get_ports {mprj_cyc_o_user}] set_load -pin_load 0.2000 [get_ports {mprj_stb_o_user}] set_load -pin_load 0.2000 [get_ports {mprj_we_o_user}] set_load -pin_load 0.2000 [get_ports {user1_vcc_powergood}] set_load -pin_load 0.2000 [get_ports {user1_vdd_powergood}] set_load -pin_load 0.2000 [get_ports {user2_vcc_powergood}] set_load -pin_load 0.2000 [get_ports {user2_vdd_powergood}] set_load -pin_load 0.2000 [get_ports {user_clock}] set_load -pin_load 0.2000 [get_ports {user_clock2}] set_load -pin_load 0.2000 [get_ports {user_reset}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[127]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[126]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[125]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[124]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[123]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[122]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[121]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[120]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[119]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[118]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[117]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[116]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[115]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[114]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[113]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[112]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[111]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[110]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[109]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[108]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[107]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[106]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[105]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[104]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[103]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[102]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[101]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[100]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[99]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[98]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[97]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[96]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[95]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[94]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[93]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[92]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[91]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[90]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[89]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[88]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[87]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[86]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[85]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[84]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[83]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[82]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[81]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[80]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[79]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[78]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[77]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[76]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[75]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[74]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[73]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[72]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[71]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[70]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[69]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[68]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[67]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[66]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[65]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[64]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[63]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[62]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[61]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[60]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[59]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[58]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[57]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[56]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[55]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[54]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[53]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[52]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[51]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[50]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[49]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[48]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[47]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[46]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[45]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[44]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[43]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[42]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[41]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[40]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[39]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[38]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[37]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[36]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[35]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[34]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[33]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[32]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[31]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[30]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[29]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[28]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[27]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[26]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[25]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[24]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[23]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[22]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[21]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[20]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[19]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[18]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[17]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[16]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[15]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[14]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[13]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[12]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[11]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[10]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[9]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[8]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[7]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[6]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[5]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[4]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[3]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[2]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[1]}] set_load -pin_load 0.2000 [get_ports {la_data_in_core[0]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[127]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[126]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[125]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[124]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[123]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[122]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[121]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[120]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[119]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[118]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[117]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[116]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[115]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[114]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[113]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[112]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[111]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[110]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[109]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[108]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[107]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[106]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[105]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[104]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[103]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[102]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[101]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[100]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[99]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[98]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[97]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[96]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[95]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[94]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[93]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[92]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[91]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[90]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[89]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[88]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[87]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[86]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[85]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[84]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[83]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[82]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[81]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[80]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[79]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[78]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[77]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[76]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[75]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[74]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[73]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[72]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[71]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[70]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[69]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[68]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[67]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[66]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[65]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[64]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[63]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[62]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[61]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[60]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[59]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[58]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[57]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[56]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[55]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[54]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[53]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[52]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[51]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[50]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[49]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[48]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[47]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[46]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[45]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[44]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[43]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[42]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[41]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[40]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[39]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[38]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[37]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[36]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[35]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[34]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[33]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[32]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[31]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[30]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[29]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[28]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[27]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[26]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[25]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[24]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[23]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[22]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[21]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[20]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[19]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[18]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[17]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[16]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[15]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[14]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[13]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[12]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[11]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[10]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[9]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[8]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[7]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[6]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[5]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[4]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[3]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[2]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[1]}] set_load -pin_load 0.2000 [get_ports {la_data_in_mprj[0]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[127]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[126]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[125]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[124]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[123]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[122]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[121]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[120]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[119]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[118]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[117]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[116]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[115]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[114]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[113]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[112]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[111]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[110]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[109]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[108]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[107]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[106]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[105]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[104]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[103]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[102]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[101]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[100]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[99]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[98]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[97]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[96]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[95]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[94]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[93]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[92]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[91]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[90]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[89]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[88]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[87]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[86]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[85]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[84]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[83]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[82]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[81]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[80]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[79]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[78]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[77]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[76]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[75]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[74]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[73]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[72]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[71]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[70]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[69]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[68]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[67]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[66]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[65]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[64]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[63]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[62]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[61]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[60]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[59]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[58]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[57]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[56]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[55]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[54]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[53]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[52]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[51]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[50]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[49]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[48]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[47]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[46]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[45]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[44]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[43]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[42]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[41]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[40]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[39]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[38]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[37]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[36]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[35]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[34]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[33]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[32]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[31]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[30]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[29]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[28]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[27]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[26]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[25]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[24]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[23]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[22]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[21]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[20]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[19]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[18]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[17]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[16]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[15]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[14]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[13]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[12]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[11]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[10]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[9]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[8]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[7]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[6]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[5]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[4]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[3]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[2]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[1]}] set_load -pin_load 0.2000 [get_ports {la_oenb_core[0]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[31]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[30]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[29]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[28]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[27]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[26]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[25]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[24]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[23]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[22]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[21]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[20]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[19]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[18]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[17]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[16]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[15]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[14]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[13]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[12]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[11]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[10]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[9]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[8]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[7]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[6]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[5]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[4]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[3]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[2]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[1]}] set_load -pin_load 0.2000 [get_ports {mprj_adr_o_user[0]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[31]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[30]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[29]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[28]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[27]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[26]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[25]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[24]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[23]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[22]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[21]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[20]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[19]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[18]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[17]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[16]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[15]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[14]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[13]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[12]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[11]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[10]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[9]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[8]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[7]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[6]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[5]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[4]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[3]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[2]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[1]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_i_core[0]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[31]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[30]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[29]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[28]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[27]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[26]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[25]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[24]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[23]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[22]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[21]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[20]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[19]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[18]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[17]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[16]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[15]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[14]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[13]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[12]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[11]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[10]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[9]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[8]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[7]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[6]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[5]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[4]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[3]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[2]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[1]}] set_load -pin_load 0.2000 [get_ports {mprj_dat_o_user[0]}] set_load -pin_load 0.2000 [get_ports {mprj_sel_o_user[3]}] set_load -pin_load 0.2000 [get_ports {mprj_sel_o_user[2]}] set_load -pin_load 0.2000 [get_ports {mprj_sel_o_user[1]}] set_load -pin_load 0.2000 [get_ports {mprj_sel_o_user[0]}] set_load -pin_load 0.2000 [get_ports {user_irq[2]}] set_load -pin_load 0.2000 [get_ports {user_irq[1]}] set_load -pin_load 0.2000 [get_ports {user_irq[0]}] ############################################################################### # Design Rules ############################################################################### set_max_transition 1.25 [current_design]