Metric,Value
design__instance__count,46948
design__instance__area,12589400
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__die__bbox,0.0 0.0 3165.0 4767.0
design__core__bbox,10.12 10.88 3154.68 4754.56
design__io,633
design__die__area,15087600
design__core__area,14916800
design__instance__count__stdcell,46854
design__instance__area__stdcell,140192
design__instance__count__macros,94
design__instance__area__macros,12449200
design__instance__utilization,0.843975
design__instance__utilization__stdcell,0.0568134
design__power_grid_violation__count__net:vccd1,8
design__power_grid_violation__count__net:vssd1,10
design__power_grid_violation__count__net:vssio,127
design__power_grid_violation__count__net:vccd,53152
design__power_grid_violation__count__net:vdda1,804
design__power_grid_violation__count__net:vssa2,870
design__power_grid_violation__count__net:vssd2,800
design__power_grid_violation__count__net:vdda2,804
design__power_grid_violation__count__net:vddio,127
design__power_grid_violation__count__net:vssd,1249
design__power_grid_violation__count__net:vccd2,804
design__power_grid_violation__count__net:vssa1,828
design__power_grid_violation__count,59583
timing__drv__floating__nets,34
timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,1617310
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
antenna__violating__nets,107
antenna__violating__pins,107
route__antenna_violation__count,107
route__net,7907
route__net__special,12
route__drc_errors__iter:1,9881
route__wirelength__iter:1,1671546
route__drc_errors__iter:2,3615
route__wirelength__iter:2,1670366
route__drc_errors__iter:3,3129
route__wirelength__iter:3,1669922
route__drc_errors__iter:4,848
route__wirelength__iter:4,1671982
route__drc_errors__iter:5,406
route__wirelength__iter:5,1671982
route__drc_errors__iter:6,311
route__wirelength__iter:6,1672038
route__drc_errors__iter:7,266
route__wirelength__iter:7,1672027
route__drc_errors__iter:8,192
route__wirelength__iter:8,1672267
route__drc_errors__iter:9,96
route__wirelength__iter:9,1672170
route__drc_errors__iter:10,69
route__wirelength__iter:10,1672235
route__drc_errors__iter:11,1
route__wirelength__iter:11,1672299
route__drc_errors__iter:12,1
route__wirelength__iter:12,1672302
route__drc_errors__iter:13,0
route__wirelength__iter:13,1672308
route__drc_errors,0
route__wirelength,1672308
route__vias,62823
route__vias__singlecut,62823
route__vias__multicut,0
design__disconnected_pin__count,4
design__critical_disconnected_pin__count,0
route__wirelength__max,4055.92
design__max_slew_violation__count__corner:nom_tt_025C_1v80,88
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2732
design__max_cap_violation__count__corner:nom_tt_025C_1v80,27
power__internal__total,0.005174397025257349
power__switching__total,0.009033364243805408
power__leakage__total,0.0000018623289861352532
power__total,0.014209624379873276
clock__skew__worst_hold__corner:nom_tt_025C_1v80,7.544759
clock__skew__worst_setup__corner:nom_tt_025C_1v80,8.099279
timing__hold__ws__corner:nom_tt_025C_1v80,0.24937
timing__setup__ws__corner:nom_tt_025C_1v80,4.266059
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.24937
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,6.117834
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,686
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2732
design__max_cap_violation__count__corner:nom_ss_100C_1v60,578
clock__skew__worst_hold__corner:nom_ss_100C_1v60,10.131796
clock__skew__worst_setup__corner:nom_ss_100C_1v60,11.207791
timing__hold__ws__corner:nom_ss_100C_1v60,0.490234
timing__setup__ws__corner:nom_ss_100C_1v60,0.477664
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.666247
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,0.477664
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,88
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2732
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,27
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,6.409457
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,6.716522
timing__hold__ws__corner:nom_ff_n40C_1v95,0.115054
timing__setup__ws__corner:nom_ff_n40C_1v95,5.555556
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.115054
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,8.421376
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,1413
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,16
design__max_fanout_violation__count__corner:min_tt_025C_1v80,2732
design__max_cap_violation__count__corner:min_tt_025C_1v80,4
clock__skew__worst_hold__corner:min_tt_025C_1v80,7.366073
clock__skew__worst_setup__corner:min_tt_025C_1v80,7.892606
timing__hold__ws__corner:min_tt_025C_1v80,0.25943
timing__setup__ws__corner:min_tt_025C_1v80,4.518233
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0.0
timing__setup__wns__corner:min_tt_025C_1v80,0.0
timing__hold_vio__count__corner:min_tt_025C_1v80,0
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.25943
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,6.463109
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,39
design__max_fanout_violation__count__corner:min_ss_100C_1v60,2732
design__max_cap_violation__count__corner:min_ss_100C_1v60,91
clock__skew__worst_hold__corner:min_ss_100C_1v60,9.851759
clock__skew__worst_setup__corner:min_ss_100C_1v60,10.882171
timing__hold__ws__corner:min_ss_100C_1v60,0.641937
timing__setup__ws__corner:min_ss_100C_1v60,1.114103
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0.0
timing__setup__wns__corner:min_ss_100C_1v60,0.0
timing__hold_vio__count__corner:min_ss_100C_1v60,0
timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.663174
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,1.114103
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,16
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2732
design__max_cap_violation__count__corner:min_ff_n40C_1v95,4
clock__skew__worst_hold__corner:min_ff_n40C_1v95,6.278924
clock__skew__worst_setup__corner:min_ff_n40C_1v95,6.565427
timing__hold__ws__corner:min_ff_n40C_1v95,0.122159
timing__setup__ws__corner:min_ff_n40C_1v95,5.775887
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.122159
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,8.628211
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,1413
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,111
design__max_fanout_violation__count__corner:max_tt_025C_1v80,2732
design__max_cap_violation__count__corner:max_tt_025C_1v80,32
clock__skew__worst_hold__corner:max_tt_025C_1v80,7.71846
clock__skew__worst_setup__corner:max_tt_025C_1v80,8.301414
timing__hold__ws__corner:max_tt_025C_1v80,0.235833
timing__setup__ws__corner:max_tt_025C_1v80,3.997819
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0.0
timing__setup__wns__corner:max_tt_025C_1v80,0.0
timing__hold_vio__count__corner:max_tt_025C_1v80,0
timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.235833
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,5.915514
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,1413
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,1705
design__max_fanout_violation__count__corner:max_ss_100C_1v60,2732
design__max_cap_violation__count__corner:max_ss_100C_1v60,1435
clock__skew__worst_hold__corner:max_ss_100C_1v60,10.385975
clock__skew__worst_setup__corner:max_ss_100C_1v60,11.50234
timing__hold__ws__corner:max_ss_100C_1v60,0.373463
timing__setup__ws__corner:max_ss_100C_1v60,0.073893
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0.0
timing__setup__wns__corner:max_ss_100C_1v60,0.0
timing__hold_vio__count__corner:max_ss_100C_1v60,0
timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.670588
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,0.073893
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timing__unannotated_net__count__corner:max_ss_100C_1v60,1413
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,111
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2732
design__max_cap_violation__count__corner:max_ff_n40C_1v95,32
clock__skew__worst_hold__corner:max_ff_n40C_1v95,6.533941
clock__skew__worst_setup__corner:max_ff_n40C_1v95,6.861891
timing__hold__ws__corner:max_ff_n40C_1v95,0.102694
timing__setup__ws__corner:max_ff_n40C_1v95,5.30355
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.102694
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,8.293603
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timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
design__max_slew_violation__count,1705
design__max_fanout_violation__count,2732
design__max_cap_violation__count,1435
clock__skew__worst_hold,10.385975
clock__skew__worst_setup,6.565427
timing__hold__ws,0.102694
timing__setup__ws,0.073893
timing__hold__tns,0.0
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timing__hold__wns,0.0
timing__setup__wns,0.0
timing__hold_vio__count,0
timing__hold_r2r__ws,0.102694
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timing__setup_r2r_vio__count,0
timing__unannotated_net__count,1413
timing__unannotated_net_filtered__count,0
design__xor_difference__count,0
magic__drc_error__count,55
klayout__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,3
design__lvs_net_difference__count,2
design__lvs_property_fail__count,0
design__lvs_error__count,196
design__lvs_unmatched_device__count,21
design__lvs_unmatched_net__count,93
design__lvs_unmatched_pin__count,77