- status: 0 - openlane design prep
  runtime_s: 1.79
  runtime_ts: 0h0m1s790ms
- status: 1 - synthesis - yosys
  runtime_s: 1.24
  runtime_ts: 0h0m1s241ms
- status: 2 - sta - openroad
  runtime_s: 0.43
  runtime_ts: 0h0m0s428ms
- status: 3 - floorplan initialization - openroad
  runtime_s: 0.55
  runtime_ts: 0h0m0s552ms
- status: 4 - ioplace - openroad
  runtime_s: 0.42
  runtime_ts: 0h0m0s422ms
- status: 5 - tap/decap insertion - openroad
  runtime_s: 0.44
  runtime_ts: 0h0m0s444ms
- status: 6 - pdn generation - openroad
  runtime_s: 0.46
  runtime_ts: 0h0m0s457ms
- status: 7 - global placement - openroad
  runtime_s: 0.57
  runtime_ts: 0h0m0s570ms
- status: 8 - detailed placement - openroad
  runtime_s: 0.47
  runtime_ts: 0h0m0s470ms
- status: 9 - detailed placement - openroad
  runtime_s: 0.47
  runtime_ts: 0h0m0s472ms
- status: 11 - write verilog - openroad
  runtime_s: 0.42
  runtime_ts: 0h0m0s418ms
- status: 11 - global routing - openroad
  runtime_s: 0.52
  runtime_ts: 0h0m0s517ms
- status: 12 - fill insertion - openroad
  runtime_s: 0.48
  runtime_ts: 0h0m0s483ms
- status: 13 - detailed_routing - openroad
  runtime_s: 1.81
  runtime_ts: 0h0m1s806ms
- status: 14 - wire lengths - openlane
  runtime_s: 0.26
  runtime_ts: 0h0m0s262ms
- status: 15 - parasitics extraction - openroad
  runtime_s: 0.46
  runtime_ts: 0h0m0s462ms
- status: 16 - sta - openroad
  runtime_s: 1.54
  runtime_ts: 0h0m1s542ms
- status: 17 - parasitics extraction - openroad
  runtime_s: 0.45
  runtime_ts: 0h0m0s454ms
- status: 18 - sta - openroad
  runtime_s: 1.55
  runtime_ts: 0h0m1s551ms
- status: 19 - parasitics extraction - openroad
  runtime_s: 0.45
  runtime_ts: 0h0m0s447ms
- status: 20 - sta - openroad
  runtime_s: 1.54
  runtime_ts: 0h0m1s536ms
- status: 21 - sta - openroad
  runtime_s: 0.39
  runtime_ts: 0h0m0s392ms
- status: 22 - ir drop report - openroad
  runtime_s: 0.42
  runtime_ts: 0h0m0s424ms
- status: 23 - gdsii - magic
  runtime_s: 1.38
  runtime_ts: 0h0m1s383ms
- status: 24 - gdsii - klayout
  runtime_s: 0.44
  runtime_ts: 0h0m0s438ms
- status: 25 - xor - klayout
  runtime_s: 0.41
  runtime_ts: 0h0m0s415ms
- status: 26 - spice extraction - magic
  runtime_s: 0.44
  runtime_ts: 0h0m0s441ms
- status: 28 - write verilog - openroad
  runtime_s: 0.4
  runtime_ts: 0h0m0s403ms
- status: 28 - write powered verilog - openlane
  runtime_s: 0.52
  runtime_ts: 0h0m0s517ms
- status: 29 - lvs - netgen
  runtime_s: 0.1
  runtime_ts: 0h0m0s102ms
- status: 30 - drc - magic
  runtime_s: 1.18
  runtime_ts: 0h0m1s175ms
- status: 31 - antenna check - openroad
  runtime_s: 0.46
  runtime_ts: 0h0m0s458ms
- status: 32 - erc - circuit validity checker
  runtime_s: 0.13
  runtime_ts: 0h0m0s133ms
---
- status: routed
  runtime_s: 12.0
  runtime_ts: 0h0m12s0ms
- status: flow completed
  runtime_s: 26.0
  runtime_ts: 0h0m26s0ms