[INFO]: Run Directory: /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/caravel_core/runs/23_03_05_23_15
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[INFO]: Running Synthesis (log: caravel_core/runs/23_03_05_23_15/logs/synthesis/1-synthesis.log)...
[INFO]: Running Single-Corner Static Timing Analysis (log: caravel_core/runs/23_03_05_23_15/logs/synthesis/2-sta.log)...
[INFO]: Running Initial Floorplanning (log: caravel_core/runs/23_03_05_23_15/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 3144.56 and height 4743.68.
[INFO]: Applying DEF template...
[INFO]: Performing Manual Macro Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/4-macro_placement.log)...
[INFO]: Performing Manual Macro Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/5-macro_placement.log)...
[INFO]: Running Tap/Decap Insertion (log: caravel_core/runs/23_03_05_23_15/logs/floorplan/6-tap.log)...
[INFO]: Applying Routing Obstructions (log: caravel_core/runs/23_03_05_23_15/logs/routing/7-obs.log)...
[INFO]: Applying Routing Obstructions (log: caravel_core/runs/23_03_05_23_15/logs/routing/8-obs.log)...
[INFO]: Power planning with power {vccd vccd1 vccd2 vdda1 vdda2 vddio} and ground {vssd vssd1 vssd2 vssa1 vssa2 vssio}...
[INFO]: Generating PDN (log: caravel_core/runs/23_03_05_23_15/logs/floorplan/9-pdn.log)...
[INFO]: Running Global Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/10-global.log)...
[INFO]: Running Placement Resizer Design Optimizations (log: caravel_core/runs/23_03_05_23_15/logs/placement/11-resizer.log)...
[INFO]: Running Detailed Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/12-detailed.log)...
[INFO]: Running Clock Tree Synthesis (log: caravel_core/runs/23_03_05_23_15/logs/cts/13-cts.log)...
[INFO]: Running Global Routing Resizer Timing Optimizations (log: caravel_core/runs/23_03_05_23_15/logs/routing/14-resizer.log)...
[INFO]: Running Global Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/15-global.log)...
[INFO]: Running Placement Resizer Design Optimizations (log: caravel_core/runs/23_03_05_23_15/logs/placement/16-resizer.log)...
[INFO]: Running Detailed Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/17-detailed.log)...
[INFO]: Running Clock Tree Synthesis (log: caravel_core/runs/23_03_05_23_15/logs/cts/18-cts.log)...
[INFO]: Running Placement Resizer Timing Optimizations (log: caravel_core/runs/23_03_05_23_15/logs/cts/19-resizer.log)...
[INFO]: Running Global Routing Resizer Timing Optimizations (log: caravel_core/runs/23_03_05_23_15/logs/routing/20-resizer.log)...
[INFO]: Running Diode Insertion (log: caravel_core/runs/23_03_05_23_15/logs/routing/21-diodes.log)...
[INFO]: Running Detailed Placement (log: caravel_core/runs/23_03_05_23_15/logs/routing/22-diode_legalization.log)...
[INFO]: Applying Routing Obstructions (log: caravel_core/runs/23_03_05_23_15/logs/routing/23-obs.log)...
[INFO]: Running Global Routing (log: caravel_core/runs/23_03_05_23_15/logs/routing/24-global.log)...
[INFO]: Starting OpenROAD Antenna Repair Iterations...
[INFO]: Starting antenna repair iteration 1 with 3 violations...
[INFO]: [Iteration 1] Failed to reduce antenna violations (3 -> 3), stopping iterations...
[INFO]: Writing Verilog (log: caravel_core/runs/23_03_05_23_15/logs/routing/24-global_write_netlist.log)...
[INFO]: Running Fill Insertion (log: caravel_core/runs/23_03_05_23_15/logs/routing/26-fill.log)...
[INFO]: Performing Manual Macro Placement (log: caravel_core/runs/23_03_05_23_15/logs/placement/27-macro_placement.log)...
[INFO]: Running Detailed Routing (log: caravel_core/runs/23_03_05_23_15/logs/routing/28-detailed.log)...
[INFO]: Checking Wire Lengths (log: caravel_core/runs/23_03_05_23_15/logs/routing/29-wire_lengths.log)...
[INFO]: Running SPEF Extraction at the min process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/30-parasitics_extraction.min.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/31-rcx_mcsta.min.log)...
[INFO]: Running SPEF Extraction at the max process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/32-parasitics_extraction.max.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/33-rcx_mcsta.max.log)...
[INFO]: Running SPEF Extraction at the nom process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/34-parasitics_extraction.nom.log)...
[INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/35-rcx_mcsta.nom.log)...
[INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: caravel_core/runs/23_03_05_23_15/logs/signoff/36-rcx_sta.log)...
[INFO]: Creating IR Drop Report (log: caravel_core/runs/23_03_05_23_15/logs/signoff/37-irdrop.log)...
[INFO]: Running OpenROAD Antenna Rule Checker (log: caravel_core/runs/23_03_05_23_15/logs/signoff/38-antenna.log)...
[INFO]: Running Magic to generate various views...
[INFO]: Streaming out GDSII with Magic (log: caravel_core/runs/23_03_05_23_15/logs/signoff/39-gdsii.log)...
[INFO]: Generating MAGLEF views...
[INFO]: Running Magic DRC (log: caravel_core/runs/23_03_05_23_15/logs/signoff/40-drc.log)...
[INFO]: Converting Magic DRC database to various tool-readable formats...
[INFO]: Saving current set of views in 'caravel_core/runs/23_03_05_23_15/results/final'...
[INFO]: Saving current set of views in '..'...
[INFO]: Saving runtime environment...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'caravel_core/runs/23_03_05_23_15/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'caravel_core/runs/23_03_05_23_15/reports/metrics.csv'.
[WARNING]: There are max slew violations in the design at the typical corner. Please refer to 'caravel_core/runs/23_03_05_23_15/reports/signoff/36-rcx_sta.slew.rpt'.
[WARNING]: There are max fanout violations in the design at the typical corner. Please refer to 'caravel_core/runs/23_03_05_23_15/reports/signoff/36-rcx_sta.slew.rpt'.
[INFO]: There are no hold violations in the design at the typical corner.
[INFO]: There are no setup violations in the design at the typical corner.
[SUCCESS]: Flow complete.
[INFO]: Note that the following warnings have been generated: