design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/caravel_core,caravel_core,23_03_05_23_15,flow completed,1h40m17s0ms,-1,3149.0854548666102,15.087555,1574.5427274333051,18.84,9057.16,23756,0,0,0,0,0,0,13,72,-1,-1,-1,4432674,403860,-50.9,-22.64,-24.83,-24.98,0.0,-7517.87,-1837.07,-2148.84,-2251.22,0.0,3815910083.0,0.0,23.8,22.45,4.89,3.5,1.65,16946,40270,4063,26506,0,0,0,21208,852,36,445,493,2745,738,98,4383,6959,7530,15,8532,67559,0,76091,14916786.380800001,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,25.0,40.0,25,6,1,50,360,264,0.22,0.28,sky130_fd_sc_hd,18,DELAY 1