{ "_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address", "_comment2": "Base address is the first element and called first address", "_not_used_currently":["0x34",[["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]], "0x30",[["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]], "SPI":{ "base_addr": ["SPI_BASE_ADR",638582784], "0x00": [["SPI status",null,0,8,"undefined",0,0,0]], "0x06": [["Manufacturer ID",["mfgr_id",11,8],0,4,"RO",4,4,1]], "0x05": [["Manufacturer ID",["mfgr_id",7,0],0,8,"RO",86,86,2]], "0x04": [["Manufacturer ID",["prod_id",7,0],0,8,"RO",17,17,3]], "0x0b": [["User project ID",["mask_rev",31,24],0,8,"RO",0,0,4]], "0x0a": [["User project ID",["mask_rev",23,16],0,8,"RO",0,0,5]], "0x09": [["User project ID",["mask_rev",15,8],0,8,"RO",0,0,6]], "0x08": [["User project ID",["mask_rev",7,0],0,8,"RO",0,0,7]], "0x0c": [["PLL enables","pll_ena",0,1,"RW",0,0,8],["PLL DCO enables","pll_dco_ena",1,1,"RW",1,1,8]], "0x10": [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]], "0x14": [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]], "0x18": [["CPU reset","reset_reg",0,1,"RW",0,0,11]], "0x28": [["CPU trap","trap",0,1,"NA",0,0,12]], "0x1c": [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]], "0x1d": [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]], "0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]], "0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]], "0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]], "0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]] }, "GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208], "0x00": [["xfer","serial_xfer",0,1,"RW",0,0,19],["bit bang enable","serial_bb_enable",1,1,"RW",0,0,19], ["bit bang reset","serial_bb_resetn",2,1,"RW",0,0,19],["bit bang load","serial_bb_load",3,1,"RW",0,0,19], ["bit bang clock","serial_bb_clock",4,1,"RW",0,0,19],["bit bang data1","serial_bb_data_1",5,1,"RW",0,0,19], ["bit bang data1","serial_bb_data_2",6,1,"RW",0,0,19]], "0x04": [["GPIO power control (reg_mprj_pwr)","pwr_ctrl_out",0,4,"RW",0,0,110]], "0x0c": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",7,0],0,8,"RW",0,0,109]], "0x0d": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",15,8],0,8,"RW",0,0,108]], "0x0e": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",23,16],0,8,"RW",0,0,107]], "0x0f": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",31,24],0,8,"RW",0,0,106]], "0x10": [["GPIO data high(reg_mprj_datah)",["mgmt_gpio_data",37,32],0,5,"RW",0,0,105]], "0x24": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",7,0],0,8,"RW",3,3,30]], "0x25": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",12,8],0,5,"RW",24,24,29]], "0x28": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",7,0],0,8,"RW",3,3,32]], "0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]], "0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]], "0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]], "0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",1,1,36]], "0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",8,8,35]], "0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]], "0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]], "0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]], "0x39": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",12,8],0,5,"RW",4,4,39]], "0x3c": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",7,0],0,8,"RW",3,3,42]], "0x3d": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",12,8],0,5,"RW",4,4,41]], "0x40": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",7,0],0,8,"RW",3,3,44]], "0x41": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",12,8],0,5,"RW",4,4,43]], "0x44": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",7,0],0,8,"RW",3,3,46]], "0x45": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",12,8],0,5,"RW",4,4,45]], "0x48": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",7,0],0,8,"RW",3,3,48]], "0x49": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",12,8],0,5,"RW",4,4,47]], "0x4c": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",7,0],0,8,"RW",3,3,50]], "0x4d": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",12,8],0,5,"RW",4,4,49]], "0x50": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",7,0],0,8,"RW",3,3,52]], "0x51": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",12,8],0,5,"RW",4,4,51]], "0x54": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",7,0],0,8,"RW",3,3,54]], "0x55": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",12,8],0,5,"RW",4,4,53]], "0x58": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",7,0],0,8,"RW",3,3,56]], "0x59": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",12,8],0,5,"RW",4,4,55]], "0x5c": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",7,0],0,8,"RW",3,3,58]], "0x5d": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",12,8],0,5,"RW",4,4,57]], "0x60": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",7,0],0,8,"RW",3,3,60]], "0x61": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",12,8],0,5,"RW",4,4,59]], "0x64": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",7,0],0,8,"RW",3,3,62]], "0x65": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",12,8],0,5,"RW",4,4,61]], "0x68": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",7,0],0,8,"RW",3,3,64]], "0x69": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",12,8],0,5,"RW",4,4,63]], "0x6c": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",7,0],0,8,"RW",3,3,66]], "0x6d": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",12,8],0,5,"RW",4,4,65]], "0x70": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",7,0],0,8,"RW",3,3,68]], "0x71": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",12,8],0,5,"RW",4,4,67]], "0x74": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",7,0],0,8,"RW",3,3,70]], "0x75": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",12,8],0,5,"RW",4,4,69]], "0x78": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",7,0],0,8,"RW",3,3,72]], "0x79": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",12,8],0,5,"RW",4,4,71]], "0x7c": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",7,0],0,8,"RW",3,3,74]], "0x7d": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",12,8],0,5,"RW",4,4,73]], "0x80": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",7,0],0,8,"RW",3,3,76]], "0x81": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",12,8],0,5,"RW",4,4,75]], "0x84": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",7,0],0,8,"RW",3,3,78]], "0x85": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",12,8],0,5,"RW",4,4,77]], "0x88": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",7,0],0,8,"RW",3,3,80]], "0x89": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",12,8],0,5,"RW",4,4,79]], "0x8c": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",7,0],0,8,"RW",3,3,82]], "0x8d": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",12,8],0,5,"RW",4,4,81]], "0x90": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",7,0],0,8,"RW",3,3,84]], "0x91": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",12,8],0,5,"RW",4,4,83]], "0x94": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",7,0],0,8,"RW",3,3,86]], "0x95": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",12,8],0,5,"RW",4,4,85]], "0x98": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",7,0],0,8,"RW",3,3,88]], "0x99": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",12,8],0,5,"RW",4,4,87]], "0x9c": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",7,0],0,8,"RW",3,3,90]], "0x9d": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",12,8],0,5,"RW",4,4,89]], "0xa0": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",7,0],0,8,"RW",3,3,92]], "0xa1": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",12,8],0,5,"RW",4,4,91]], "0xa4": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",7,0],0,8,"RW",3,3,94]], "0xa5": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",12,8],0,5,"RW",4,4,93]], "0xa8": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",7,0],0,8,"RW",3,3,96]], "0xa9": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",12,8],0,5,"RW",4,4,95]], "0xac": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",7,0],0,8,"RW",3,3,98]], "0xad": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",12,8],0,5,"RW",4,4,97]], "0xb0": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",7,0],0,8,"RW",3,3,100]], "0xb1": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",12,8],0,5,"RW",4,4,99]], "0xb4": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",7,0],0,8,"RW",3,3,102]], "0xb5": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",12,8],0,5,"RW",24,24,101]], "0xb8": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",7,0],0,8,"RW",3,3,104]], "0xb9": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",12,8],0,5,"RW",24,24,103]] }, "sys":{ "base_addr": ["SYS_BASE_ADR",639631360], "0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"NA",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"NA",0,0,26], ["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]], "0x04": [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27], ["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27], ["clock1 output redirect","clk1_output_dest",2,1,"RW",0,0,27]], "0x0c": [["IRQ1 input redirect","irq_1_inputsrc",0,1,"RW",0,0,28],["IRQ2 redirect","irq_2_inputsrc",1,1,"RW",0,0,28]], "0x10": [["Housekeeping SPI disable","hkspi_disable",0,1,"RW",0,0,111]] } }