design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/openlane/designs/housekeeping,housekeeping,CARAVEL_3,flow completed,0h27m39s0ms,0h9m48s0ms,-2.0,0.20397821850000003,-1,27.46,1920.61,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,537830,74553,0.0,-0.06,0.0,0.0,0.0,0.0,-0.06,0.0,0.0,0.0,335718259.0,0.0,59.79,79.59,27.73,54.13,10.77,8363,9422,189,1195,0,0,0,9086,156,1,144,323,4521,44,5,170,942,889,20,388,2646,0,3034,189331.584,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,AREA 0,20,50,1,153.6,153.18,0.28,0.3,sky130_fd_sc_hd,3