# Run configs
set ::env(PDK_ROOT) {/pdk}
set ::env(BASE_SDC_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/sdc_files/base.sdc}
set ::env(BOTTOM_MARGIN_MULT) {4}
set ::env(CARRY_SELECT_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
set ::env(CELLS_LEF) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
set ::env(CELLS_LEF_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
set ::env(CELL_CLK_PORT) {CLK}
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
set ::env(CLK_BUFFER_INPUT) {A}
set ::env(CLK_BUFFER_OUTPUT) {X}
set ::env(CLOCK_BUFFER_FANOUT) {16}
set ::env(CLOCK_NET) {caravel_clk}
set ::env(CLOCK_PERIOD) {25}
set ::env(CLOCK_PORT) {clock_core}
set ::env(CLOCK_TREE_SYNTH) {1}
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
set ::env(CORE_AREA) {10 10 3155 4757}
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4}
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {1000}
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
set ::env(CTS_MAX_CAP) {0.3}
set ::env(CTS_REPORT_TIMING) {1}
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {30}
set ::env(CTS_SINK_CLUSTERING_SIZE) {12}
set ::env(CTS_SQR_CAP) {0.258e-3}
set ::env(CTS_SQR_RES) {0.125}
set ::env(CTS_TARGET_SKEW) {200}
set ::env(CTS_TECH_DIR) {N/A}
set ::env(CTS_TOLERANCE) {100}
set ::env(CVC_SCRIPTS_DIR) {/pdk/sky130A/libs.tech/openlane/cvc}
set ::env(DATA_WIRE_RC_LAYER) {met2}
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
set ::env(DEFAULT_MAX_TRAN) {0.75}
set ::env(DEF_UNITS_PER_MICRON) {1000}
set ::env(DESIGN_CONFIG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/config.tcl}
set ::env(DESIGN_IS_CORE) {1}
set ::env(DESIGN_NAME) {caravel_core}
set ::env(DETAILED_ROUTER) {tritonroute}
set ::env(DIE_AREA) {0 0 3165 4767}
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
set ::env(DIODE_CELL_PIN) {DIODE}
set ::env(DIODE_ON_PORTS) {none}
set ::env(DIODE_PADDING) {0}
set ::env(DPL_CELL_PADDING) {0}
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/drc_exclude.cells}
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
set ::env(DRT_OPT_ITERS) {64}
set ::env(EXTRA_GDS_FILES) { /home/hosni/caravel-redesign-2/caravel/gds/user_id_programming.gds  /home/hosni/caravel-redesign-2/caravel/gds/user_project_wrapper_empty.gds  /home/hosni/caravel-redesign-2/caravel/gds/housekeeping.gds  /home/hosni/caravel-redesign-2/caravel/gds/simple_por.gds  /home/hosni/caravel-redesign-2/caravel/gds/xres_buf.gds  /home/hosni/caravel-redesign-2/caravel/gds/spare_logic_block.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj_io_buffer.gds  /home/hosni/caravel-redesign-2/caravel/gds/gpio_defaults_block.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj2_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/mgmt_protect_hv.gds  /home/hosni/caravel-redesign-2/caravel/gds/gpio_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/empty_macro.gds  /home/hosni/caravel-redesign-2/caravel/gds/caravel_clocking.gds  /home/hosni/caravel-redesign-2/caravel/gds/manual_power_connections.gds  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/gds/RAM128.gds  }
set ::env(EXTRA_LEFS) { /home/hosni/caravel-redesign-2/caravel/lef/user_id_programming.lef  /home/hosni/caravel-redesign-2/caravel/lef/user_project_wrapper_empty.lef  /home/hosni/caravel-redesign-2/caravel/lef/housekeeping.lef  /home/hosni/caravel-redesign-2/caravel/lef/simple_por.lef  /home/hosni/caravel-redesign-2/caravel/lef/xres_buf.lef  /home/hosni/caravel-redesign-2/caravel/lef/spare_logic_block.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj_io_buffer.lef  /home/hosni/caravel-redesign-2/caravel/lef/gpio_defaults_block.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj2_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/mgmt_protect_hv.lef  /home/hosni/caravel-redesign-2/caravel/lef/gpio_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/empty_macro.lef  /home/hosni/caravel-redesign-2/caravel/lef/caravel_clocking.lef  /home/hosni/caravel-redesign-2/caravel/lef/manual_power_connections.lef  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/lef/RAM128.lef  }
set ::env(EXTRA_LIBS) { /home/hosni/caravel-redesign-2/caravel/lib/housekeeping.lib  /home/hosni/caravel-redesign-2/caravel/lib/gpio_defaults_block.lib  /home/hosni/caravel-redesign-2/caravel/lib/gpio_logic_high.lib  /home/hosni/caravel-redesign-2/caravel/lib/mprj_io_buffer.lib  /home/hosni/caravel-redesign-2/caravel/lib/user_project_wrapper.lib  /home/hosni/caravel-redesign-2/caravel/lib/caravel_clocking.lib  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/signoff/RAM128/primetime/lib/ff/RAM128.nom.lib  }
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
set ::env(FP_ASPECT_RATIO) {1}
set ::env(FP_CORE_UTIL) {50}
set ::env(FP_DEF_TEMPLATE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/io.def}
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
set ::env(FP_IO_HEXTEND) {2}
set ::env(FP_IO_HLAYER) {met3}
set ::env(FP_IO_HLENGTH) {4}
set ::env(FP_IO_HTHICKNESS_MULT) {2}
set ::env(FP_IO_MIN_DISTANCE) {5}
set ::env(FP_IO_MODE) {1}
set ::env(FP_IO_UNMATCHED_ERROR) {1}
set ::env(FP_IO_VEXTEND) {2}
set ::env(FP_IO_VLAYER) {met2}
set ::env(FP_IO_VLENGTH) {4}
set ::env(FP_IO_VTHICKNESS_MULT) {2}
set ::env(FP_PDN_AUTO_ADJUST) {1}
set ::env(FP_PDN_CHECK_NODES) {0}
set ::env(FP_PDN_CORE_RING) {1}
set ::env(FP_PDN_CORE_RING_HOFFSET) {0}
set ::env(FP_PDN_CORE_RING_HSPACING) {2}
set ::env(FP_PDN_CORE_RING_HWIDTH) {10}
set ::env(FP_PDN_CORE_RING_VOFFSET) {0}
set ::env(FP_PDN_CORE_RING_VSPACING) {2}
set ::env(FP_PDN_CORE_RING_VWIDTH) {10}
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_ENABLE_RAILS) {1}
set ::env(FP_PDN_HOFFSET) {30.65}
set ::env(FP_PDN_HORIZONTAL_HALO) {1}
set ::env(FP_PDN_HPITCH) {360}
set ::env(FP_PDN_HSPACING) {27}
set ::env(FP_PDN_HWIDTH) {3}
set ::env(FP_PDN_IRDROP) {1}
set ::env(FP_PDN_LOWER_LAYER) {met4}
set ::env(FP_PDN_MACRO_HOOKS) {
    user_id_value vccd vssd VPWR VGND, housekeeping vccd vssd VPWR VGND, mprj vccd1 vssd1 vccd1 vssd1, mprj vccd2 vssd2 vccd2 vssd2, mprj vdda1 vssa1 vdda1 vssa1, mprj vdda2 vssa2 vdda2 vssa2, soc.core.RAM256.BANK128\\\\\\[0\\\\\\].RAM128 vccd vssd VPWR VGND, soc.core.RAM256.BANK128\\\\\\[1\\\\\\].RAM128 vccd vssd VPWR VGND, soc.core.RAM0 vccd vssd vccd1 vssd1, mgmt_buffers.mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1, mgmt_buffers.mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2, mgmt_buffers.powergood_check vccd vssd vccd vssd, mgmt_buffers.powergood_check vdda1 vssa1 vdda1 vssa1, mgmt_buffers.powergood_check vdda2 vssa2 vdda2 vssa2, gpio_control_bidir_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[11\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[12\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[13\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[14\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[15\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, spare_logic\\\\\\[0\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[1\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[2\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[3\\\\\\] vccd vssd vccd vssd, clock_ctrl vccd vssd VPWR VGND, por vddio vssio vdd3v3 vss3v3, por vccd vssd vdd1v8 vss1v8, rstb_level vddio vssio VPWR VGND, rstb_level vccd vssd LVPWR LVGND }
set ::env(FP_PDN_RAILS_LAYER) {met1}
set ::env(FP_PDN_RAIL_OFFSET) {0}
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
set ::env(FP_PDN_SKIPTRIM) {0}
set ::env(FP_PDN_UPPER_LAYER) {met5}
set ::env(FP_PDN_VERTICAL_HALO) {8}
set ::env(FP_PDN_VOFFSET) {3.5}
set ::env(FP_PDN_VPITCH) {264}
set ::env(FP_PDN_VSPACING) {19}
set ::env(FP_PDN_VWIDTH) {3}
set ::env(FP_PIN_ORDER_CFG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/pin_order.cfg}
set ::env(FP_SIZING) {absolute}
set ::env(FP_TAPCELL_DIST) {10}
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
set ::env(FP_TAP_VERTICAL_HALO) {10}
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
set ::env(FULL_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
set ::env(GDS_FILES) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
set ::env(GDS_FILES_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
set ::env(GLB_CFG_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/config.tcl}
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(GLB_RESIZER_DESIGN_OPTIMIZATIONS) {1}
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {30}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {30}
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {600}
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {1}
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(GLOBAL_ROUTER) {fastroute}
set ::env(GND_NETS) {vssd vssd1 vssd2 vssa1 vssa2 vssio}
set ::env(GND_PIN) {VGND}
set ::env(GND_PIN_VOLTAGE) {0.00}
set ::env(GPIO_PADS_LEF) { /pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
set ::env(GPIO_PADS_PREFIX) {sky130_fd_io sky130_ef_io}
set ::env(GPIO_PADS_VERILOG) { /pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
}
set ::env(GPL_CELL_PADDING) {0}
set ::env(GRT_ADJUSTMENT) {0.10}
set ::env(GRT_ALLOW_CONGESTION) {1}
set ::env(GRT_ANT_ITERS) {12}
set ::env(GRT_ANT_MARGIN) {10}
set ::env(GRT_ESTIMATE_PARASITICS) {1}
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
set ::env(GRT_MACRO_EXTENSION) {0}
set ::env(GRT_MAX_DIODE_INS_ITERS) {4}
set ::env(GRT_OVERFLOW_ITERS) {50}
set ::env(GRT_REPAIR_ANTENNAS) {1}
set ::env(HEURISTIC_ANTENNA_INSERTION_MODE) {source}
set ::env(HEURISTIC_ANTENNA_THRESHOLD) {80}
set ::env(IO_PCT) {0.2}
set ::env(KLAYOUT_DEF_LAYER_MAP) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.map}
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/pdk/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
set ::env(KLAYOUT_PROPERTIES) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyp}
set ::env(KLAYOUT_TECH) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyt}
set ::env(KLAYOUT_XOR_GDS) {1}
set ::env(KLAYOUT_XOR_IGNORE_LAYERS) {81/14}
set ::env(KLAYOUT_XOR_THREADS) {1}
set ::env(KLAYOUT_XOR_XML) {1}
set ::env(LEC_ENABLE) {0}
set ::env(LEFT_MARGIN_MULT) {12}
set ::env(LIB_FASTEST) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
set ::env(LIB_SLOWEST) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
set ::env(LIB_SLOWEST_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
set ::env(LIB_SYNTH) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(LIB_TYPICAL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(LOGS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs}
set ::env(LVS_CONNECT_BY_LABEL) {0}
set ::env(LVS_INSERT_POWER_PINS) {1}
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
set ::env(MACRO_PLACEMENT_CFG_1) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_1.cfg}
set ::env(MACRO_PLACEMENT_CFG_2) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_2.cfg}
set ::env(MACRO_PLACEMENT_CFG_3) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_3.cfg}
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
set ::env(MAGIC_DEF_LABELS) {0}
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
set ::env(MAGIC_DRC_USE_GDS) {1}
set ::env(MAGIC_EXT_USE_GDS) {1}
set ::env(MAGIC_GDS_ALLOW_ABSTRACT) {0}
set ::env(MAGIC_GDS_POLYGON_SUBCELLS) {0}
set ::env(MAGIC_GENERATE_GDS) {1}
set ::env(MAGIC_GENERATE_LEF) {1}
set ::env(MAGIC_GENERATE_MAGLEF) {1}
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
set ::env(MAGIC_MAGICRC) {/pdk/sky130A/libs.tech/magic/sky130A.magicrc}
set ::env(MAGIC_PAD) {0}
set ::env(MAGIC_TECH_FILE) {/pdk/sky130A/libs.tech/magic/sky130A.tech}
set ::env(MAGIC_WRITE_FULL_LEF) {0}
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
set ::env(NETGEN_SETUP_FILE) {/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl}
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/no_synth.cells}
set ::env(OPENLANE_VERBOSE) {0}
set ::env(PDKPATH) {/pdk/sky130A}
set ::env(PDN_CFG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/pdn_configuration/pdn.tcl}
set ::env(PLACE_SITE) {unithd}
set ::env(PLACE_SITE_HEIGHT) {2.720}
set ::env(PLACE_SITE_WIDTH) {0.460}
set ::env(PL_BASIC_PLACEMENT) {0}
set ::env(PL_ESTIMATE_PARASITICS) {1}
set ::env(PL_LIB) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(PL_MACRO_CHANNEL) {0 0}
set ::env(PL_MACRO_HALO) {-1 -3}
set ::env(PL_MAX_DISPLACEMENT_X) {500}
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
set ::env(PL_OPTIMIZE_MIRRORING) {1}
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {1}
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.03}
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {50}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {50}
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {1000}
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.1}
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(PL_ROUTABILITY_DRIVEN) {0}
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
set ::env(PL_TARGET_DENSITY) {0.24}
set ::env(PL_TIME_DRIVEN) {1}
set ::env(PL_WIRELENGTH_COEF) {0.01}
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
set ::env(PROCESS) {130}
set ::env(QUIT_ON_ASSIGN_STATEMENTS) {0}
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
set ::env(QUIT_ON_LONG_WIRE) {0}
set ::env(QUIT_ON_LVS_ERROR) {0}
set ::env(QUIT_ON_MAGIC_DRC) {0}
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
set ::env(QUIT_ON_SYNTH_CHECKS) {0}
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
set ::env(QUIT_ON_TR_DRC) {1}
set ::env(QUIT_ON_UNMAPPED_CELLS) {1}
set ::env(QUIT_ON_XOR_ERROR) {1}
set ::env(RCX_CC_MODEL) {10}
set ::env(RCX_CONTEXT_DEPTH) {5}
set ::env(RCX_CORNER_COUNT) {1}
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
set ::env(RCX_MAX_RESISTANCE) {50}
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
set ::env(RCX_RULES) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
set ::env(RCX_RULES_MAX) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
set ::env(RCX_RULES_MIN) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
set ::env(RCX_SDC_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/sdc_files/rcx.sdc}
set ::env(REPORTS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports}
set ::env(RESULTS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results}
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
set ::env(RIGHT_MARGIN_MULT) {12}
set ::env(RIPPLE_CARRY_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
set ::env(ROUTING_CORES) {36}
set ::env(RSZ_DONT_TOUCH_RX) {analog_io|rstb_h|porb_h|serial_clock_out|serial_load_out|ringosc|mgmt_buffers.la_data_out_core|mprj_ack_i_user|mprj_dat_i_user|user_irq_core}
set ::env(RSZ_USE_OLD_REMOVER) {0}
set ::env(RT_MAX_LAYER) {met5}
set ::env(RT_MIN_LAYER) {met1}
set ::env(RUN_CVC) {1}
set ::env(RUN_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44}
set ::env(RUN_DRT) {1}
set ::env(RUN_FILL_INSERTION) {1}
set ::env(RUN_HEURISTIC_DIODE_INSERTION) {1}
set ::env(RUN_IRDROP_REPORT) {1}
set ::env(RUN_KLAYOUT) {0}
set ::env(RUN_KLAYOUT_DRC) {0}
set ::env(RUN_KLAYOUT_XOR) {1}
set ::env(RUN_LVS) {1}
set ::env(RUN_MAGIC) {1}
set ::env(RUN_MAGIC_DRC) {1}
set ::env(RUN_SPEF_EXTRACTION) {1}
set ::env(RUN_TAG) {23_04_20_20_44}
set ::env(RUN_TAP_DECAP_INSERTION) {1}
set ::env(SCLPATH) {/pdk/sky130A/sky130_fd_sc_hd}
set ::env(SPEF_EXTRACTOR) {openrcx}
set ::env(START_TIME) {2023.04.21_03.44.58}
set ::env(STA_REPORT_POWER) {1}
set ::env(STA_WRITE_LIB) {0}
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
set ::env(STD_CELL_LIBRARY_CDL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
set ::env(SYNTH_BIN) {yosys}
set ::env(SYNTH_BUFFERING) {0}
set ::env(SYNTH_CAP_LOAD) {52}
set ::env(SYNTH_CLOCK_TRANSITION) {0.6}
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
set ::env(SYNTH_ELABORATE_ONLY) {0}
set ::env(SYNTH_EXTRA_MAPPING_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/yosys_mapping.v}
set ::env(SYNTH_FLAT_TOP) {0}
set ::env(SYNTH_LATCH_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
set ::env(SYNTH_MAX_FANOUT) {12}
set ::env(SYNTH_MAX_TRAN) {0.50}
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
set ::env(SYNTH_MUX4_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
set ::env(SYNTH_MUX_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
set ::env(SYNTH_NO_FLAT) {0}
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
set ::env(SYNTH_SHARE_RESOURCES) {1}
set ::env(SYNTH_SIZING) {0}
set ::env(SYNTH_STRATEGY) {DELAY 1}
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
set ::env(SYNTH_TIMING_DERATE) {0.05}
set ::env(TAKE_LAYOUT_SCROT) {0}
set ::env(TECH_LEF) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
set ::env(TECH_LEF_MAX) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
set ::env(TECH_LEF_MIN) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
set ::env(TECH_LEF_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
set ::env(TERMINAL_OUTPUT) {/dev/null}
set ::env(TMP_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp}
set ::env(TOP_MARGIN_MULT) {4}
set ::env(TRACKS_INFO_FILE) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
set ::env(TRISTATE_BUFFER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
set ::env(USE_ARC_ANTENNA_CHECK) {1}
set ::env(USE_GPIO_PADS) {0}
set ::env(VDD_NETS) {vccd vccd1 vccd2 vdda1 vdda2 vddio}
set ::env(VDD_PIN) {VPWR}
set ::env(VDD_PIN_VOLTAGE) {1.80}
set ::env(VERILOG_FILES) { /home/hosni/caravel-redesign-2/caravel/verilog/rtl/defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/user_defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/caravel_core.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mgmt_protect.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/digital_pll.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/clock_div.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_control_block.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/mgmt_core_wrapper.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/mgmt_core.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/ibex_all.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/picorv32.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/VexRiscv_MinDebugCache.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/RAM256.v  }
set ::env(VERILOG_FILES_BLACKBOX) { /home/hosni/caravel-redesign-2/caravel/verilog/rtl/defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/user_id_programming.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/__user_project_wrapper.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/housekeeping.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/simple_por.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/xres_buf.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/spare_logic_block.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/mprj_io_buffer.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_defaults_block.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mprj_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mprj2_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mgmt_protect_hv.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/empty_macro.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/caravel_clocking.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/manual_power_connections.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/gl/RAM128.v  }
set ::env(VSRC_LOC) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/Vsrc.loc}
set ::env(WIRE_RC_LAYER) {met1}
set ::env(YOSYS_REWRITE_VERILOG) {0}
set ::env(cts_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/cts}
set ::env(cts_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/cts}
set ::env(cts_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/cts}
set ::env(cts_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/cts}
set ::env(floorplan_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/floorplan}
set ::env(floorplan_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/floorplan}
set ::env(floorplan_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/floorplan}
set ::env(floorplan_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/floorplan}
set ::env(placement_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/placement}
set ::env(placement_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/placement}
set ::env(placement_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/placement}
set ::env(placement_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/placement}
set ::env(routing_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/routing}
set ::env(routing_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/routing}
set ::env(routing_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing}
set ::env(routing_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing}
set ::env(signoff_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/signoff}
set ::env(signoff_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/signoff}
set ::env(signoff_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/signoff}
set ::env(signoff_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/signoff}
set ::env(synthesis_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/synthesis}
set ::env(synthesis_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/synthesis}
set ::env(synthesis_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/synthesis}
set ::env(synthesis_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis}
set ::env(CURRENT_INDEX) 44
set ::env(CURRENT_DEF) /home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.def
set ::env(CURRENT_GUIDE) /home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing/30-global.guide
set ::env(CURRENT_NETLIST) /home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.nl.v
set ::env(CURRENT_POWERED_NETLIST) {0}
set ::env(CURRENT_ODB) /home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.odb
set ::env(PDK_ROOT) {/pdk}
set ::env(ANTENNA_VIOLATOR_LIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/signoff/43-antenna_violators.rpt}
set ::env(BASE_SDC_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/sdc_files/base.sdc}
set ::env(BASIC_PREP_COMPLETE) {1}
set ::env(BOTTOM_MARGIN_MULT) {4}
set ::env(CARAVEL_ROOT) {/home/hosni/caravel-redesign-2/caravel}
set ::env(CARRY_SELECT_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
set ::env(CELLS_LEF) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
set ::env(CELLS_LEF_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /pdk/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
set ::env(CELL_CLK_PORT) {CLK}
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
set ::env(CLK_BUFFER_INPUT) {A}
set ::env(CLK_BUFFER_OUTPUT) {X}
set ::env(CLOCK_BUFFER_FANOUT) {16}
set ::env(CLOCK_NET) {caravel_clk}
set ::env(CLOCK_PERIOD) {25}
set ::env(CLOCK_PORT) {clock_core}
set ::env(CLOCK_TREE_SYNTH) {1}
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
set ::env(CORE_AREA) {10.12 10.88 3154.68 4754.56}
set ::env(CORE_HEIGHT) {4743.68}
set ::env(CORE_WIDTH) {3144.56}
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4}
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {1000}
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
set ::env(CTS_MAX_CAP) {0.3}
set ::env(CTS_REPORT_TIMING) {1}
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {30}
set ::env(CTS_SINK_CLUSTERING_SIZE) {12}
set ::env(CTS_SQR_CAP) {0.258e-3}
set ::env(CTS_SQR_RES) {0.125}
set ::env(CTS_TARGET_SKEW) {200}
set ::env(CTS_TECH_DIR) {N/A}
set ::env(CTS_TOLERANCE) {100}
set ::env(CURRENT_DEF) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.def}
set ::env(CURRENT_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing}
set ::env(CURRENT_GUIDE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing/30-global.guide}
set ::env(CURRENT_INDEX) {44}
set ::env(CURRENT_NETLIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.nl.v}
set ::env(CURRENT_ODB) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.odb}
set ::env(CURRENT_POWERED_NETLIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/caravel_core.pnl.v}
set ::env(CURRENT_SDC) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/cts/caravel_core.sdc}
set ::env(CURRENT_SDF) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/mca/process_corner_nom/caravel_core.sdf}
set ::env(CURRENT_SPEF) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/mca/process_corner_nom/caravel_core.spef}
set ::env(CVC_SCRIPTS_DIR) {/pdk/sky130A/libs.tech/openlane/cvc}
set ::env(DATA_WIRE_RC_LAYER) {met2}
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
set ::env(DEFAULT_MAX_TRAN) {0.75}
set ::env(DEF_UNITS_PER_MICRON) {1000}
set ::env(DESIGN_CONFIG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/config.tcl}
set ::env(DESIGN_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core}
set ::env(DESIGN_IS_CORE) {1}
set ::env(DESIGN_NAME) {caravel_core}
set ::env(DETAILED_ROUTER) {tritonroute}
set ::env(DIE_AREA) {0.0 0.0 3165.0 4767.0}
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
set ::env(DIODE_CELL_PIN) {DIODE}
set ::env(DIODE_ON_PORTS) {none}
set ::env(DIODE_PADDING) {0}
set ::env(DONT_USE_CELLS) {sky130_fd_sc_hd__a2111oi_0 sky130_fd_sc_hd__a21boi_0 sky130_fd_sc_hd__and2_0 sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__fa_4 sky130_fd_sc_hd__lpflow_bleeder_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_16 sky130_fd_sc_hd__lpflow_clkbufkapwr_2 sky130_fd_sc_hd__lpflow_clkbufkapwr_4 sky130_fd_sc_hd__lpflow_clkbufkapwr_8 sky130_fd_sc_hd__lpflow_clkinvkapwr_1 sky130_fd_sc_hd__lpflow_clkinvkapwr_16 sky130_fd_sc_hd__lpflow_clkinvkapwr_2 sky130_fd_sc_hd__lpflow_clkinvkapwr_4 sky130_fd_sc_hd__lpflow_clkinvkapwr_8 sky130_fd_sc_hd__lpflow_decapkapwr_12 sky130_fd_sc_hd__lpflow_decapkapwr_3 sky130_fd_sc_hd__lpflow_decapkapwr_4 sky130_fd_sc_hd__lpflow_decapkapwr_6 sky130_fd_sc_hd__lpflow_decapkapwr_8 sky130_fd_sc_hd__lpflow_inputiso0n_1 sky130_fd_sc_hd__lpflow_inputiso0p_1 sky130_fd_sc_hd__lpflow_inputiso1n_1 sky130_fd_sc_hd__lpflow_inputiso1p_1 sky130_fd_sc_hd__lpflow_inputisolatch_1 sky130_fd_sc_hd__lpflow_isobufsrc_1 sky130_fd_sc_hd__lpflow_isobufsrc_16 sky130_fd_sc_hd__lpflow_isobufsrc_2 sky130_fd_sc_hd__lpflow_isobufsrc_4 sky130_fd_sc_hd__lpflow_isobufsrc_8 sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 sky130_fd_sc_hd__mux4_4 sky130_fd_sc_hd__o21ai_0 sky130_fd_sc_hd__o311ai_0 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__probe_p_8 sky130_fd_sc_hd__probec_p_8 sky130_fd_sc_hd__xor3_1 sky130_fd_sc_hd__xor3_2 sky130_fd_sc_hd__xor3_4 sky130_fd_sc_hd__xnor3_1 sky130_fd_sc_hd__xnor3_2 sky130_fd_sc_hd__xnor3_4 sky130_fd_sc_hd__a2111oi_1 sky130_fd_sc_hd__a211o_1 sky130_fd_sc_hd__a211oi_1 sky130_fd_sc_hd__a2111o_1 sky130_fd_sc_hd__a21bo_1 sky130_fd_sc_hd__a21boi_1 sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1 sky130_fd_sc_hd__a221o_1 sky130_fd_sc_hd__a221oi_1 sky130_fd_sc_hd__a222oi_1 sky130_fd_sc_hd__a22o_1 sky130_fd_sc_hd__a22oi_1 sky130_fd_sc_hd__a2bb2o_1 sky130_fd_sc_hd__a2bb2oi_1 sky130_fd_sc_hd__a311o_1 sky130_fd_sc_hd__a311oi_1 sky130_fd_sc_hd__a2111o_1 sky130_fd_sc_hd__a21bo_1 sky130_fd_sc_hd__a21boi_1 sky130_fd_sc_hd__a21o_1 sky130_fd_sc_hd__a21oi_1 sky130_fd_sc_hd__a221o_1 sky130_fd_sc_hd__a221oi_1 sky130_fd_sc_hd__a222oi_1 sky130_fd_sc_hd__a22o_1 sky130_fd_sc_hd__a22oi_1 sky130_fd_sc_hd__a2bb2o_1 sky130_fd_sc_hd__a2bb2oi_1 sky130_fd_sc_hd__a311o_1 sky130_fd_sc_hd__a311oi_1 sky130_fd_sc_hd__a31o_1 sky130_fd_sc_hd__a31oi_1 sky130_fd_sc_hd__a32o_1 sky130_fd_sc_hd__a32oi_1 sky130_fd_sc_hd__a41o_1 sky130_fd_sc_hd__a41oi_1 sky130_fd_sc_hd__and2_1 sky130_fd_sc_hd__and2b_1 sky130_fd_sc_hd__and3_1 sky130_fd_sc_hd__and3b_1 sky130_fd_sc_hd__and4_1 sky130_fd_sc_hd__and4b_1 sky130_fd_sc_hd__and4bb_1 sky130_fd_sc_hd__dfbbn_1 sky130_fd_sc_hd__dfbbp_1 sky130_fd_sc_hd__dfrbp_1 sky130_fd_sc_hd__dfrtn_1 sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfsbp_1 sky130_fd_sc_hd__dfstp_1 sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__nand2_1 sky130_fd_sc_hd__nand2b_1 sky130_fd_sc_hd__nand3_1 sky130_fd_sc_hd__nand3b_1 sky130_fd_sc_hd__nand4_1 sky130_fd_sc_hd__nand4b_1 sky130_fd_sc_hd__nand4bb_1 sky130_fd_sc_hd__nor2_1 sky130_fd_sc_hd__nor2b_1 sky130_fd_sc_hd__nor3_1 sky130_fd_sc_hd__nor3b_1 sky130_fd_sc_hd__nor4_1 sky130_fd_sc_hd__nor4b_1 sky130_fd_sc_hd__nor4bb_1 sky130_fd_sc_hd__o2111a_1 sky130_fd_sc_hd__o2111ai_1 sky130_fd_sc_hd__o211a_1 sky130_fd_sc_hd__o211ai_1 sky130_fd_sc_hd__o21a_1 sky130_fd_sc_hd__o21ai_1 sky130_fd_sc_hd__o21ba_1 sky130_fd_sc_hd__o21bai_1 sky130_fd_sc_hd__o221a_1 sky130_fd_sc_hd__o221ai_1 sky130_fd_sc_hd__o22a_1 sky130_fd_sc_hd__o22ai_1 sky130_fd_sc_hd__o2bb2a_1 sky130_fd_sc_hd__o2bb2ai_1 sky130_fd_sc_hd__o311a_1 sky130_fd_sc_hd__o311ai_1 sky130_fd_sc_hd__o31a_1 sky130_fd_sc_hd__o31ai_1 sky130_fd_sc_hd__o32a_1 sky130_fd_sc_hd__o32ai_1 sky130_fd_sc_hd__o41a_1 sky130_fd_sc_hd__o41ai_1 sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2b_1 sky130_fd_sc_hd__or3_1 sky130_fd_sc_hd__or3b_1 sky130_fd_sc_hd__or4_1 sky130_fd_sc_hd__or4b_1 sky130_fd_sc_hd__or4bb_1 sky130_fd_sc_hd__xnor2_1 sky130_fd_sc_hd__xor2_1 sky130_fd_sc_hd__or2 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1 sky130_fd_sc_hd__or2_2 sky130_fd_sc_hd__or2_4 sky130_fd_sc_hd__or2b sky130_fd_sc_hd__or2b_1 sky130_fd_sc_hd__or2b_2 sky130_fd_sc_hd__or2b_4 sky130_fd_sc_hd__or3 sky130_fd_sc_hd__or3_1 sky130_fd_sc_hd__or3_2 sky130_fd_sc_hd__or3_4 sky130_fd_sc_hd__or3b sky130_fd_sc_hd__or3b_1 sky130_fd_sc_hd__or3b_2 sky130_fd_sc_hd__or3b_4 sky130_fd_sc_hd__or4 sky130_fd_sc_hd__or4_1 sky130_fd_sc_hd__or4_2 sky130_fd_sc_hd__or4_4 sky130_fd_sc_hd__or4b sky130_fd_sc_hd__or4b_1 sky130_fd_sc_hd__or4b_2 sky130_fd_sc_hd__or4b_4 sky130_fd_sc_hd__or4bb sky130_fd_sc_hd__or4bb_1 sky130_fd_sc_hd__or4bb_2 sky130_fd_sc_hd__or4bb_4 sky130_fd_sc_hd__inv_2 sky130_fd_sc_hd__a21boi_0 sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__bufbuf_1 sky130_fd_sc_hd__bufinv_1 sky130_fd_sc_hd__clkbuf_1 sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__clkdlybuf4s25_1 sky130_fd_sc_hd__clkdlybuf4s25_2 sky130_fd_sc_hd__clkdlybuf4s50_1 sky130_fd_sc_hd__clkdlybuf4s50_2 sky130_fd_sc_hd__clkinv_1 sky130_fd_sc_hd__dlygate4sd1_1 sky130_fd_sc_hd__dlygate4sd2_1 sky130_fd_sc_hd__dlygate4sd2_2 sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__dlygate4sd3_2 sky130_fd_sc_hd__dlymetal6s2s_1 sky130_fd_sc_hd__dlymetal6s4s_1 sky130_fd_sc_hd__dlymetal6s4s_2 sky130_fd_sc_hd__dlymetal6s6s_1 sky130_fd_sc_hd__dlymetal6s6s_2 sky130_fd_sc_hd__a22oi_4 sky130_fd_sc_hd__a22oi_2 sky130_fd_sc_hd__a22oi_1 sky130_fd_sc_hd__and2_2 }
set ::env(DPL_CELL_PADDING) {0}
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/drc_exclude.cells}
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
set ::env(DRT_OPT_ITERS) {64}
set ::env(EXIT_ON_ERROR) {1}
set ::env(EXTRA_GDS_FILES) { /home/hosni/caravel-redesign-2/caravel/gds/user_id_programming.gds  /home/hosni/caravel-redesign-2/caravel/gds/user_project_wrapper_empty.gds  /home/hosni/caravel-redesign-2/caravel/gds/housekeeping.gds  /home/hosni/caravel-redesign-2/caravel/gds/simple_por.gds  /home/hosni/caravel-redesign-2/caravel/gds/xres_buf.gds  /home/hosni/caravel-redesign-2/caravel/gds/spare_logic_block.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj_io_buffer.gds  /home/hosni/caravel-redesign-2/caravel/gds/gpio_defaults_block.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/mprj2_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/mgmt_protect_hv.gds  /home/hosni/caravel-redesign-2/caravel/gds/gpio_logic_high.gds  /home/hosni/caravel-redesign-2/caravel/gds/empty_macro.gds  /home/hosni/caravel-redesign-2/caravel/gds/caravel_clocking.gds  /home/hosni/caravel-redesign-2/caravel/gds/manual_power_connections.gds  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/gds/RAM128.gds  }
set ::env(EXTRA_LEFS) { /home/hosni/caravel-redesign-2/caravel/lef/user_id_programming.lef  /home/hosni/caravel-redesign-2/caravel/lef/user_project_wrapper_empty.lef  /home/hosni/caravel-redesign-2/caravel/lef/housekeeping.lef  /home/hosni/caravel-redesign-2/caravel/lef/simple_por.lef  /home/hosni/caravel-redesign-2/caravel/lef/xres_buf.lef  /home/hosni/caravel-redesign-2/caravel/lef/spare_logic_block.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj_io_buffer.lef  /home/hosni/caravel-redesign-2/caravel/lef/gpio_defaults_block.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/mprj2_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/mgmt_protect_hv.lef  /home/hosni/caravel-redesign-2/caravel/lef/gpio_logic_high.lef  /home/hosni/caravel-redesign-2/caravel/lef/empty_macro.lef  /home/hosni/caravel-redesign-2/caravel/lef/caravel_clocking.lef  /home/hosni/caravel-redesign-2/caravel/lef/manual_power_connections.lef  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/lef/RAM128.lef  }
set ::env(EXTRA_LIBS) { /home/hosni/caravel-redesign-2/caravel/lib/housekeeping.lib  /home/hosni/caravel-redesign-2/caravel/lib/gpio_defaults_block.lib  /home/hosni/caravel-redesign-2/caravel/lib/gpio_logic_high.lib  /home/hosni/caravel-redesign-2/caravel/lib/mprj_io_buffer.lib  /home/hosni/caravel-redesign-2/caravel/lib/user_project_wrapper.lib  /home/hosni/caravel-redesign-2/caravel/lib/caravel_clocking.lib  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/signoff/RAM128/primetime/lib/ff/RAM128.nom.lib  }
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
set ::env(FP_ASPECT_RATIO) {1}
set ::env(FP_CORE_UTIL) {50}
set ::env(FP_DEF_TEMPLATE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/io.def}
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
set ::env(FP_IO_HEXTEND) {2}
set ::env(FP_IO_HLAYER) {met3}
set ::env(FP_IO_HLENGTH) {4}
set ::env(FP_IO_HTHICKNESS_MULT) {2}
set ::env(FP_IO_MIN_DISTANCE) {5}
set ::env(FP_IO_MODE) {1}
set ::env(FP_IO_UNMATCHED_ERROR) {1}
set ::env(FP_IO_VEXTEND) {2}
set ::env(FP_IO_VLAYER) {met2}
set ::env(FP_IO_VLENGTH) {4}
set ::env(FP_IO_VTHICKNESS_MULT) {2}
set ::env(FP_PDN_AUTO_ADJUST) {1}
set ::env(FP_PDN_CHECK_NODES) {0}
set ::env(FP_PDN_CORE_RING) {1}
set ::env(FP_PDN_CORE_RING_HOFFSET) {0}
set ::env(FP_PDN_CORE_RING_HSPACING) {2}
set ::env(FP_PDN_CORE_RING_HWIDTH) {10}
set ::env(FP_PDN_CORE_RING_VOFFSET) {0}
set ::env(FP_PDN_CORE_RING_VSPACING) {2}
set ::env(FP_PDN_CORE_RING_VWIDTH) {10}
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_ENABLE_RAILS) {1}
set ::env(FP_PDN_HOFFSET) {30.65}
set ::env(FP_PDN_HORIZONTAL_HALO) {1}
set ::env(FP_PDN_HPITCH) {360}
set ::env(FP_PDN_HSPACING) {27}
set ::env(FP_PDN_HWIDTH) {3}
set ::env(FP_PDN_IRDROP) {1}
set ::env(FP_PDN_LOWER_LAYER) {met4}
set ::env(FP_PDN_MACRO_HOOKS) {
    user_id_value vccd vssd VPWR VGND, housekeeping vccd vssd VPWR VGND, mprj vccd1 vssd1 vccd1 vssd1, mprj vccd2 vssd2 vccd2 vssd2, mprj vdda1 vssa1 vdda1 vssa1, mprj vdda2 vssa2 vdda2 vssa2, soc.core.RAM256.BANK128\\\\\\[0\\\\\\].RAM128 vccd vssd VPWR VGND, soc.core.RAM256.BANK128\\\\\\[1\\\\\\].RAM128 vccd vssd VPWR VGND, soc.core.RAM0 vccd vssd vccd1 vssd1, mgmt_buffers.mprj_logic_high_inst vccd1 vssd1 vccd1 vssd1, mgmt_buffers.mprj2_logic_high_inst vccd2 vssd2 vccd2 vssd2, mgmt_buffers.powergood_check vccd vssd vccd vssd, mgmt_buffers.powergood_check vdda1 vssa1 vdda1 vssa1, mgmt_buffers.powergood_check vdda2 vssa2 vdda2 vssa2, gpio_control_bidir_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1a\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_1\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[3\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[4\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[5\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[6\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[7\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[8\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[9\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[10\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[11\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[12\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[13\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[14\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_in_2\\\\\\[15\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[0\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[1\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, gpio_control_bidir_2\\\\\\[2\\\\\\].gpio_logic_high vccd1 vssd1 vccd1 vssd1, spare_logic\\\\\\[0\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[1\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[2\\\\\\] vccd vssd vccd vssd, spare_logic\\\\\\[3\\\\\\] vccd vssd vccd vssd, clock_ctrl vccd vssd VPWR VGND, por vddio vssio vdd3v3 vss3v3, por vccd vssd vdd1v8 vss1v8, rstb_level vddio vssio VPWR VGND, rstb_level vccd vssd LVPWR LVGND }
set ::env(FP_PDN_RAILS_LAYER) {met1}
set ::env(FP_PDN_RAIL_OFFSET) {0}
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
set ::env(FP_PDN_SKIPTRIM) {0}
set ::env(FP_PDN_UPPER_LAYER) {met5}
set ::env(FP_PDN_VERTICAL_HALO) {8}
set ::env(FP_PDN_VOFFSET) {3.5}
set ::env(FP_PDN_VPITCH) {264}
set ::env(FP_PDN_VSPACING) {19}
set ::env(FP_PDN_VWIDTH) {3}
set ::env(FP_PIN_ORDER_CFG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/pin_order.cfg}
set ::env(FP_SIZING) {absolute}
set ::env(FP_TAPCELL_DIST) {10}
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
set ::env(FP_TAP_VERTICAL_HALO) {10}
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
set ::env(FULL_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
set ::env(GDS_FILES) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
set ::env(GDS_FILES_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
set ::env(GLB_CFG_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/config.tcl}
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(GLB_RESIZER_DESIGN_OPTIMIZATIONS) {0}
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {30}
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {30}
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {600}
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {1}
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
set ::env(GLOBAL_ROUTER) {fastroute}
set ::env(GND_NET) {vssd}
set ::env(GND_NETS) {vssd vssd1 vssd2 vssa1 vssa2 vssio}
set ::env(GND_PIN) {vssd}
set ::env(GND_PIN_VOLTAGE) {0.00}
set ::env(GPIO_PADS_LEF) { /pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /pdk/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /pdk/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
set ::env(GPIO_PADS_PREFIX) {sky130_fd_io sky130_ef_io}
set ::env(GPIO_PADS_VERILOG) { /pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
}
set ::env(GPL_CELL_PADDING) {0}
set ::env(GRT_ADJUSTMENT) {0.10}
set ::env(GRT_ALLOW_CONGESTION) {0}
set ::env(GRT_ANT_ITERS) {12}
set ::env(GRT_ANT_MARGIN) {10}
set ::env(GRT_ESTIMATE_PARASITICS) {1}
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
set ::env(GRT_MACRO_EXTENSION) {0}
set ::env(GRT_MAX_DIODE_INS_ITERS) {4}
set ::env(GRT_OBS) { met5 90 175.0 496.18 612.92,  met5 582.00 175.00 988.18 612.92,  met5 1800 125.00 2206.18 562.92,  met5 2650 190 3060.23 740.95,  met4 90 175.0 496.18 612.92,  met4 582.00 175.00 988.18 612.92,  met4 1800 125.00 2206.18 562.92,  met4 2650 190 3060.23 740.95  }
set ::env(GRT_OVERFLOW_ITERS) {50}
set ::env(GRT_REPAIR_ANTENNAS) {1}
set ::env(HEURISTIC_ANTENNA_INSERTION_MODE) {source}
set ::env(HEURISTIC_ANTENNA_THRESHOLD) {80}
set ::env(HOME) {/}
set ::env(HOSTNAME) {9193a2ebfbcc}
set ::env(IO_PCT) {0.2}
set ::env(KLAYOUT_DEF_LAYER_MAP) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.map}
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/pdk/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
set ::env(KLAYOUT_PROPERTIES) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyp}
set ::env(KLAYOUT_TECH) {/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyt}
set ::env(KLAYOUT_XOR_GDS) {1}
set ::env(KLAYOUT_XOR_IGNORE_LAYERS) {81/14}
set ::env(KLAYOUT_XOR_THREADS) {1}
set ::env(KLAYOUT_XOR_XML) {1}
set ::env(LANG) {en_US.UTF-8}
set ::env(LAST_TIMING_REPORT_TAG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/signoff/42-rcx_sta}
set ::env(LC_ALL) {en_US.UTF-8}
set ::env(LC_CTYPE) {en_US.UTF-8}
set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
set ::env(LEC_ENABLE) {0}
set ::env(LEFT_MARGIN_MULT) {12}
set ::env(LIB_CTS) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/cts/cts.lib}
set ::env(LIB_FASTEST) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
set ::env(LIB_SLOWEST) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
set ::env(LIB_SLOWEST_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
set ::env(LIB_SYNTH) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis/trimmed.lib}
set ::env(LIB_SYNTH_COMPLETE) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib}
set ::env(LIB_SYNTH_MERGED) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis/merged.lib}
set ::env(LIB_SYNTH_NO_PG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis/1-trimmed.no_pg.lib}
set ::env(LIB_TYPICAL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(LOGS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs}
set ::env(LVS_CONNECT_BY_LABEL) {0}
set ::env(LVS_INSERT_POWER_PINS) {1}
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
set ::env(MACRO_PLACEMENT_CFG_1) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_1.cfg}
set ::env(MACRO_PLACEMENT_CFG_2) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_2.cfg}
set ::env(MACRO_PLACEMENT_CFG_3) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/macro_placement_3.cfg}
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
set ::env(MAGIC_DEF_LABELS) {0}
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
set ::env(MAGIC_DRC_USE_GDS) {1}
set ::env(MAGIC_EXT_USE_GDS) {1}
set ::env(MAGIC_GDS_ALLOW_ABSTRACT) {0}
set ::env(MAGIC_GDS_POLYGON_SUBCELLS) {0}
set ::env(MAGIC_GENERATE_GDS) {1}
set ::env(MAGIC_GENERATE_LEF) {1}
set ::env(MAGIC_GENERATE_MAGLEF) {1}
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
set ::env(MAGIC_MAGICRC) {/pdk/sky130A/libs.tech/magic/sky130A.magicrc}
set ::env(MAGIC_PAD) {0}
set ::env(MAGIC_TECH_FILE) {/pdk/sky130A/libs.tech/magic/sky130A.tech}
set ::env(MAGIC_WRITE_FULL_LEF) {0}
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
set ::env(MAGTYPE) {maglef}
set ::env(MANPATH) {/build//share/man:}
set ::env(MAX_METAL_LAYER) {6}
set ::env(MCW_ROOT) {/home/hosni/caravel_sky130/caravel_mgmt_soc_litex}
set ::env(MC_SDF_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/mca/sdf}
set ::env(MC_SPEF_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing/mca/spef}
set ::env(MERGED_LEF) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/merged.nom.lef}
set ::env(MERGED_LEF_MAX) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/merged.max.lef}
set ::env(MERGED_LEF_MIN) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/merged.min.lef}
set ::env(MISMATCHES_OK) {1}
set ::env(NETGEN_SETUP_FILE) {/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl}
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/no_synth.cells}
set ::env(OPENLANE_MOUNTED_SCRIPTS_VERSION) {d70884942e62945c564c7c5c23daea9d7ae58cce}
set ::env(OPENLANE_ROOT) {/openlane}
set ::env(OPENLANE_RUN_TAG) {23_04_20_20_44}
set ::env(OPENLANE_VERBOSE) {0}
set ::env(OPENLANE_VERSION) {05fac72e4dcbaab8d56151495e1c77f29db1e576}
set ::env(OPENROAD) {/build/}
set ::env(OPENROAD_BIN) {openroad}
set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
set ::env(PDK) {sky130A}
set ::env(PDKPATH) {/pdk/sky130A}
set ::env(PDK_ROOT) {/pdk}
set ::env(PDN_CFG) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/pdn_configuration/pdn.tcl}
set ::env(PLACE_SITE) {unithd}
set ::env(PLACE_SITE_HEIGHT) {2.720}
set ::env(PLACE_SITE_WIDTH) {0.460}
set ::env(PL_BASIC_PLACEMENT) {0}
set ::env(PL_ESTIMATE_PARASITICS) {1}
set ::env(PL_INIT_COEFF) {0.00002}
set ::env(PL_IO_ITER) {5}
set ::env(PL_LIB) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(PL_MACRO_CHANNEL) {0 0}
set ::env(PL_MACRO_HALO) {-1 -3}
set ::env(PL_MAX_DISPLACEMENT_X) {500}
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
set ::env(PL_OPTIMIZE_MIRRORING) {1}
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.03}
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {50}
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {50}
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {1000}
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.1}
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
set ::env(PL_ROUTABILITY_DRIVEN) {0}
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
set ::env(PL_TARGET_DENSITY) {0.29}
set ::env(PL_TIME_DRIVEN) {1}
set ::env(PL_WIRELENGTH_COEF) {0.01}
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
set ::env(PROCESS) {130}
set ::env(PWD) {/home/hosni/caravel-redesign-2/caravel/openlane}
set ::env(QUIT_ON_ASSIGN_STATEMENTS) {0}
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
set ::env(QUIT_ON_LONG_WIRE) {0}
set ::env(QUIT_ON_LVS_ERROR) {0}
set ::env(QUIT_ON_MAGIC_DRC) {0}
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
set ::env(QUIT_ON_SYNTH_CHECKS) {0}
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
set ::env(QUIT_ON_TR_DRC) {1}
set ::env(QUIT_ON_UNMAPPED_CELLS) {1}
set ::env(QUIT_ON_XOR_ERROR) {1}
set ::env(RCX_CC_MODEL) {10}
set ::env(RCX_CONTEXT_DEPTH) {5}
set ::env(RCX_CORNER_COUNT) {1}
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
set ::env(RCX_MAX_RESISTANCE) {50}
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
set ::env(RCX_RULES) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
set ::env(RCX_RULES_MAX) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
set ::env(RCX_RULES_MIN) {/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
set ::env(RCX_SDC_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/sdc_files/rcx.sdc}
set ::env(REPORTS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports}
set ::env(RESULTS_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results}
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
set ::env(RIGHT_MARGIN_MULT) {12}
set ::env(RIPPLE_CARRY_ADDER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
set ::env(ROUTING_CORES) {36}
set ::env(RSZ_DONT_TOUCH_RX) {analog_io|rstb_h|porb_h|serial_clock_out|serial_load_out|ringosc|mgmt_buffers.la_data_out_core|mprj_ack_i_user|mprj_dat_i_user|user_irq_core}
set ::env(RSZ_LIB) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis/resizer_sky130_fd_sc_hd__tt_025C_1v80.lib}
set ::env(RSZ_USE_OLD_REMOVER) {0}
set ::env(RT_MAX_LAYER) {met5}
set ::env(RT_MIN_LAYER) {met1}
set ::env(RUN_CVC) {1}
set ::env(RUN_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44}
set ::env(RUN_DRT) {1}
set ::env(RUN_FILL_INSERTION) {1}
set ::env(RUN_HEURISTIC_DIODE_INSERTION) {1}
set ::env(RUN_IRDROP_REPORT) {1}
set ::env(RUN_KLAYOUT) {0}
set ::env(RUN_KLAYOUT_DRC) {0}
set ::env(RUN_KLAYOUT_XOR) {1}
set ::env(RUN_LVS) {1}
set ::env(RUN_MAGIC) {1}
set ::env(RUN_MAGIC_DRC) {1}
set ::env(RUN_SPEF_EXTRACTION) {1}
set ::env(RUN_STANDALONE) {1}
set ::env(RUN_TAG) {23_04_20_20_44}
set ::env(RUN_TAP_DECAP_INSERTION) {1}
set ::env(SCLPATH) {/pdk/sky130A/sky130_fd_sc_hd}
set ::env(SCRIPTS_DIR) {/openlane/scripts}
set ::env(SHLVL) {1}
set ::env(SPEF_EXTRACTOR) {openrcx}
set ::env(START_TIME) {2023.04.21_03.44.58}
set ::env(STA_PRE_CTS) {0}
set ::env(STA_REPORT_POWER) {1}
set ::env(STA_WRITE_LIB) {0}
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
set ::env(STD_CELL_LIBRARY_CDL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
set ::env(SYNTH_BIN) {yosys}
set ::env(SYNTH_BUFFERING) {0}
set ::env(SYNTH_CAP_LOAD) {52}
set ::env(SYNTH_CLOCK_TRANSITION) {0.6}
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
set ::env(SYNTH_ELABORATE_ONLY) {0}
set ::env(SYNTH_EXTRA_MAPPING_FILE) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/synth_configuration/yosys_mapping.v}
set ::env(SYNTH_FLAT_TOP) {0}
set ::env(SYNTH_LATCH_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
set ::env(SYNTH_MAX_FANOUT) {12}
set ::env(SYNTH_MAX_TRAN) {0.50}
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
set ::env(SYNTH_MUX4_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
set ::env(SYNTH_MUX_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
set ::env(SYNTH_NO_FLAT) {0}
set ::env(SYNTH_OPT) {0}
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
set ::env(SYNTH_SHARE_RESOURCES) {1}
set ::env(SYNTH_SIZING) {0}
set ::env(SYNTH_STRATEGY) {DELAY 1}
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
set ::env(SYNTH_TIMING_DERATE) {0.05}
set ::env(TAKE_LAYOUT_SCROT) {0}
set ::env(TCLLIBPATH) {/usr/share/tcl8.5 /usr/lib64/tcl8.5 /usr/lib64/tk8.5 /usr/share/tk8.5 /openlane/scripts/ /usr/share/tcl8.5/tcllib-1.14}
set ::env(TECH_LEF) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
set ::env(TECH_LEF_MAX) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
set ::env(TECH_LEF_MIN) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
set ::env(TECH_LEF_OPT) {/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
set ::env(TECH_METAL_LAYERS) {li1 met1 met2 met3 met4 met5}
set ::env(TERM) {xterm}
set ::env(TERMINAL_OUTPUT) {/dev/null}
set ::env(TMP_DIR) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp}
set ::env(TOP_MARGIN_MULT) {4}
set ::env(TRACKS_INFO_FILE) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing/config.tracks}
set ::env(TRISTATE_BUFFER_MAP) {/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
set ::env(USE_ARC_ANTENNA_CHECK) {1}
set ::env(USE_GPIO_PADS) {0}
set ::env(VCHECK_OUTPUT) {The version of openroad_app installed in the environment does not match the one required by the OpenLane flow scripts (installed: 1a1617d908d2ebdb731de9ab4e3d9fd93a6dcf97, expected: 6840b7481d49c83870f79646cf979e66f22f6833)}
set ::env(VDD_NET) {vccd}
set ::env(VDD_NETS) {vccd vccd1 vccd2 vdda1 vdda2 vddio}
set ::env(VDD_PIN) {vccd}
set ::env(VDD_PIN_VOLTAGE) {1.80}
set ::env(VERILOG_FILES) { /home/hosni/caravel-redesign-2/caravel/verilog/rtl/defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/user_defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/caravel_core.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mgmt_protect.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/digital_pll.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/clock_div.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_control_block.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/mgmt_core_wrapper.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/mgmt_core.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/ibex_all.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/picorv32.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/VexRiscv_MinDebugCache.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/rtl/RAM256.v  }
set ::env(VERILOG_FILES_BLACKBOX) { /home/hosni/caravel-redesign-2/caravel/verilog/rtl/defines.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/user_id_programming.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/__user_project_wrapper.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/housekeeping.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/simple_por.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/xres_buf.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/spare_logic_block.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/mprj_io_buffer.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_defaults_block.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mprj_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mprj2_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/mgmt_protect_hv.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/gpio_logic_high.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/empty_macro.v  /home/hosni/caravel-redesign-2/caravel/verilog/gl/caravel_clocking.v  /home/hosni/caravel-redesign-2/caravel/verilog/rtl/manual_power_connections.v  /home/hosni/caravel_sky130/caravel_mgmt_soc_litex/verilog/gl/RAM128.v  }
set ::env(VSRC_LOC) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/floorplan_configuration/Vsrc.loc}
set ::env(WIRE_RC_LAYER) {met1}
set ::env(YOSYS_REWRITE_VERILOG) {0}
set ::env(_) {/openlane/flow.tcl}
set ::env(cts_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/cts}
set ::env(cts_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/cts}
set ::env(cts_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/cts}
set ::env(cts_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/cts}
set ::env(drc_prefix) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/signoff/drc}
set ::env(floorplan_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/floorplan}
set ::env(floorplan_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/floorplan}
set ::env(floorplan_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/floorplan}
set ::env(floorplan_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/floorplan}
set ::env(fp_report_prefix) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/floorplan/3-initial_fp}
set ::env(placement_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/placement}
set ::env(placement_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/placement}
set ::env(placement_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/placement}
set ::env(placement_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/placement}
set ::env(routing_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/routing}
set ::env(routing_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/routing}
set ::env(routing_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/routing}
set ::env(routing_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/routing}
set ::env(signoff_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/signoff}
set ::env(signoff_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/signoff}
set ::env(signoff_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/signoff}
set ::env(signoff_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/signoff}
set ::env(synth_report_prefix) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/synthesis/1-synthesis}
set ::env(synthesis_logs) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/logs/synthesis}
set ::env(synthesis_reports) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/reports/synthesis}
set ::env(synthesis_results) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/results/synthesis}
set ::env(synthesis_tmpfiles) {/home/hosni/caravel-redesign-2/caravel/openlane/caravel_core/runs/23_04_20_20_44/tmp/synthesis}
set ::env(timer_end) {1682052293}
set ::env(timer_start) {1682048698}