Commit Graph

6 Commits

Author SHA1 Message Date
Tim Edwards e6169aaf8c Copied files from the original pull request into a new one. Includes
a few layout updates since the original pull request.  The openframe
design matches the user example in caravel_openframe_project.
2023-05-08 16:29:24 -04:00
Tim Edwards cca54a2a74 Final LVS run reports for caravel and caravan top levels, showing LVS
clean.  Provides the netgen report, JSON file, and run-time log of
each.  Modified the scripts to tee into the run-time log file and to
add the SPICE netlist of the simple_por.  Corrected the simple_por
netlist to make the xhigh resistors non-width-specific, since the
width-specific ID mask is not a GDS layer and cannot be reconstructed
from GDS (at least not with the current tech file in magic).
2022-11-11 15:40:08 -05:00
Tim Edwards 94461a3125 Added LVS results for caravel and scripts for running caravel and
caravan LVS using the new PDK to update the chip GDS.  Moved files
to their proper places.  Still waiting on caravan LVS result file.
2022-11-11 12:21:24 -05:00
R. Timothy Edwards d882f42803
Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90)
* Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds.
This commit does the following:
(1) Corrects the xschem simple_por schematic to separate the 1.8V and 3.3V grounds.
(2) Corrects the xschem simple_por symbol to separate the 1.8V and 3.3V grounds.
(3) Corrects the xschem testbench to connect to both grounds of simple_por.
(4) Corrects the simple_por layout to remove the 1.8V logic from the
    3.3V ground and connect it instead to the 1.8V ground.
(5) Extends the top-level power routing of caravel and caravan to
    make a better connection to the simple_por 1.8V ground.
(6) Adds an LVS script to properly check the simple_por layout against the
    xschem-generated schematic netlist.

NOTE: None of these modifications change the function of any circuit.  The
1.8V and 3.3V ground nets are only logically separated in the netlists but
share the substrate.  This fix cleanly defines the 1.8V and 3.3V grounds
within the simple_por, where they were previously mingled.  It also ensures
that the full LVS for caravel and caravan can now include the simple_por at
the transistor level and still pass.

* Updated the GDS of simple_por (previously did not remove GDS_FILE
from the .mag file and so it just overwrote the original GDS file
with itself).

* Corrected a route to simple_por in the top level of both caravel
and caravan that was shorting to the extra metals put on top of
the substrate contact across the top (bottom, in the top level)
of the simple_por layout.
2022-05-08 22:51:29 -07:00
Marwan Abbas e9f023f9fa
Introduction of PDK variable (#39)
* added PDK_VARIENT variable

* changed variable name to PDK

* resolve issue

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:05:58 -07:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest
hardened macro components into the caravel and caravan layouts.
2021-11-15 10:34:52 -05:00