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616 Commits

Author SHA1 Message Date
marwaneltoukhy fe96857e5e added gpio_defaults_block_0801.mag 2022-10-11 07:48:14 -07:00
kareem b0abb4e164 add chip_io gl 
~ update interactive script for chip_io.v for recent openlane
~ update config.tcl for recent openlane
~ add a verilog stub for sky130_fd_io__top_xres4v2 as
the io verilog models are not readable by yosys
 2022-10-11 07:35:13 -07:00
Passant 7dccb3aeb4 remove redundant makedirs 2022-10-11 05:00:12 -07:00
Marwan Abbas 8540c4fcdf Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign 2022-10-11 12:22:09 +02:00
Marwan Abbas e378a191ad fixed build script and run sta 2022-10-11 12:22:01 +02:00
Mohamed Shalan 68b7d7f99f
Merge pull request #173 from mo-hosni/caravel_redesign 
Caravel redesign
 2022-10-11 10:48:50 +02:00
Mohamed Shalan 11530f691e
Merge pull request #165 from efabless/misc-rtl-changes 
some rtl changes
 2022-10-11 10:48:18 +02:00
Mohamed Hosni ee17bcf177
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-11 01:47:06 -07:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
Mohamed Shalan fe3d2b927f
Merge pull request #139 from efabless/cocotb 
new environment for simulation automation with cocotb and vcs
 2022-10-11 10:41:22 +02:00
mo-hosni e1b2509aad update mgmt_protect gl to be powered 2022-10-11 01:40:51 -07:00
Mohamed Shalan 4f1ee965a9
Merge pull request #170 from efabless/update_por_lef 
Updated the LEF of simple_por
 2022-10-11 10:40:11 +02:00
Mohamed Shalan 344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell 
gpio_control_block sparecell
 2022-10-11 10:39:50 +02:00
Mohamed Shalan db9362d858
Merge branch 'caravel_redesign' into misc-rtl-changes 2022-10-11 10:39:32 +02:00
Tim Edwards 67a12304fa Updated the LEF of simple_por, which was generated without the 
"-hide" option, but was also missing the metals 2 and 3 over the
substrate contact, allowing routes on those layers to short to
the actual layout.  The new LEF properly reflects the current
version of the POR layout.
 2022-10-10 20:58:07 -04:00
Passant 3afdbacfdd Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign 2022-10-10 15:53:41 -07:00
Passant b3f69ba769 add creating `.lib` for the design at the end of the STA run 
add all process corners liberties for the IO cells
update spef mapping based on the updated instances names in the top-level caravel
 2022-10-10 15:46:41 -07:00
Passant ddbf9a15df update signoff sdc of the re-implemented macros 2022-10-10 15:46:02 -07:00
M0stafaRady 01a9fd928f
Fix typo at mprj_io (#168) 
* Fix typo at mprj_io

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
 2022-10-10 12:11:05 -07:00
kareem 16fba569ad updated caravel gds that was missed in the last caravel update push 2022-10-10 08:35:13 -07:00
M0stafaRady 11ce4a30eb Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-10 06:23:58 -07:00
M0stafaRady 71d53b9958 added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
kareem 70b4c07598 copy openlane run's signoff directory 2022-10-10 06:11:06 -07:00
kareem 2771b1b11a Merge branch 'gpio_control_block-sparecell' of github.com:efabless/caravel into gpio_control_block-sparecell 2022-10-10 05:59:26 -07:00
kareem f4218ddde9 reharden!: gpio_control_block 
- reimplement using a sparecell
- reimplement using newest open_pdks

!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible

!important override abstract lef generated by openlane. openlane
 generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
 2022-10-10 05:42:29 -07:00
kareefardi eab0cab8eb Apply automatic changes to Manifest and README.rst 2022-10-10 12:26:45 +00:00
kareem 3a81dde555 add sky130_fd_sc_hd__macro_sparecell inside gpio_control_block rtl 2022-10-10 05:24:25 -07:00
kareefardi 623be602c2 Apply automatic changes to Manifest and README.rst 2022-10-10 12:22:26 +00:00
kareem 71e309a923 some rtl changes 
- remove unused port in chip_io
- move the rest of chip_io power ports to the USE_POWER_PINS guard
- add caravel_power_routing cell guarded by TOP_ROUTING ifdef
 2022-10-10 05:13:48 -07:00
Mohamed Shalan cbcef378ad
Merge pull request #163 from mo-hosni/caravel_redesign 
Caravel redesign
 2022-10-10 14:13:06 +02:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
kareefardi ace9274138 Apply automatic changes to Manifest and README.rst 2022-10-10 12:07:13 +00:00
M0stafaRady 0006ae4f25 Apply automatic changes to Manifest and README.rst 2022-10-10 12:06:07 +00:00
kareem 11620eb224 Merge branch 'caravel_redesign' of github.com:efabless/caravel into caravel_redesign 2022-10-10 05:05:48 -07:00
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
kareem 285ef6b642 reharden!: caravel 
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
 2022-10-10 04:51:05 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady dd6fb6cfc4 Merge branch 'cocotb' of github.com:efabless/caravel into cocotb 2022-10-10 04:35:35 -07:00
M0stafaRady 45a885caaa update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT 2022-10-10 04:34:26 -07:00
Marwan Abbas a8934d66cc fixes for logging and sta running 2022-10-10 13:25:09 +02:00
Mohamed Shalan f5b8b0ab7c
Merge pull request #162 from efabless/chip_io_rework_update 
Update of all views of chip_io and chip_io_alt
 2022-10-10 12:18:42 +02:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
Tim Edwards 2459b3583e Updated all views of chip_io and chip_io_alt based on the abstract 
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
 2022-10-09 14:20:43 -04:00
Marwan Abbas a3dd90fc61 build script fixes 2022-10-09 20:11:42 +02:00
Marwan Abbas 943a503441 run sta in parallel with drc, lvs and verification 2022-10-09 20:10:28 +02:00
Marwan Abbas ccb9a90977 added klayout drc python script 2022-10-09 19:55:27 +02:00
Marwan Abbas 82fcb3a54d remove unnecessary prints 2022-10-09 19:43:17 +02:00
Marwan Abbas ecc06078b9 added signoff automation script + supporting scripts 2022-10-09 19:36:50 +02:00