riscv
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caravel
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4 Commits

Author SHA1 Message Date
mo-hosni e076718887 add `/// sta-blackbox` in the modules that will be blackboxed in STA 2023-05-22 05:52:27 -07:00
Tim Edwards ec93c72d18 Modified simple_por.v RTL to avoid the wire declaration that "cvc" 
doesn't like (even though it's perfectly legal).
 2021-12-08 12:16:19 -05:00
Tim Edwards e86831b188 Final edits to make caravel LVS clean. 2021-11-22 16:51:35 -05:00
Tim Edwards 332f9ec2e7 Seeding with documentation of pinout and verilog RTL (mostly unchanged 
from original except to remove blocks that are not supposed to be in
this repository like the processor core and the storage).
 2021-10-12 16:31:42 -04:00