view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
fork of caravel (layout .mag file not copied into this commit).
The layouts of both chip_io and chip_io_alt are believed to be
complete, but need verification (with LVS).
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
Fixed rstb_h, which was being input to low-voltage blocks. (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be; the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line. This should probably be addressed in
housekeeping but would change the current pinout.
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
Tim Edwards