update. Also changed the defaults block types in the layout so that
they match the gate-level netlist. This does not change the behavior
after assembly but lets LVS run correctly on the layout prior to final
assembly.
to housekeeping and the management core wrapper to separate the
wb_cyc_i signal and connect to new signal hk_cyc_o on the
management core. Also: Fixed a dangling input (user_clock) on
the housekeeping (minor error caused by the earlier refactoring
and unnoticed because there is no testbench covering that
function).
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
Tim Edwards
manarabdelaty