caravel

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	6eb8bb54de	Several more LVS corrections, including fixing a label in chip_io that got removed from its net by a chang in the LEF view of an I/O pad, and a lack of declaration of an array to attach to pwr_ctrl_out in the verilog, which is valid verilog but netgen can't know the bus size without the no-connect net being declared. The remaining issue has to do with separation of ground domains in the mgmt_protect block.	2021-11-21 22:58:39 -05:00
Tim Edwards	cd906cbf8a	Updated the copyright block for the new designs. Added caravel layout and placed the GPIO control blocks and default blocks.	2021-11-06 22:13:19 -04:00
Tim Edwards	a7148378a0	Added as many of the magic database layout files as are expected to remain unchanged between the caravel and caravel_openframe repositories.	2021-10-26 10:27:03 -04:00

Author

SHA1

Message

Date

Tim Edwards

6eb8bb54de

Several more LVS corrections, including fixing a label in chip_io that

got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.

2021-11-21 22:58:39 -05:00

Tim Edwards

cd906cbf8a

Updated the copyright block for the new designs. Added caravel

layout and placed the GPIO control blocks and default blocks.

2021-11-06 22:13:19 -04:00

Tim Edwards

a7148378a0

Added as many of the magic database layout files as are expected to remain

unchanged between the caravel and caravel_openframe repositories.

2021-10-26 10:27:03 -04:00

3 Commits