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caravel
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935 Commits 140 Branches 61 Tags 15 GiB
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23 Commits

Author SHA1 Message Date
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
mo-hosni 3f0bddbcc6 update openlane views 2022-10-16 03:45:30 -07:00
kareem 3e3bd111c1 ~ correct paths refereces in mag and maglef files from openlane 2022-10-15 04:06:07 -07:00
mo-hosni 0e01725608 add housekeeping views 2022-10-14 09:26:34 -07:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
mo-hosni 9c850bf94b rehardened housekeeping 2022-10-05 12:35:03 -07:00
Tim Edwards 1b3fe4379c Corrected the placement of the isosub layer in the layouts so that 
it is exactly overlapping;  this resolves issues with LVS.  Also:
Corrected the references to the OpenLane/ path in the .mag files
by changing them to the canonical $PDKPATH reference.
 2021-12-24 22:22:23 -05:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
Tim Edwards e2ee74c591 Changed "simple_por" in both caravel and caravan to be an abstract 
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
 2021-11-27 11:51:30 -05:00
Tim Edwards f67f7b6daf Corrected bad paths on two layouts in mag/ and most of the layouts 
in maglef/, all of which were erroneously pointing to paths in
either OpenLane or the user's home directory path.
 2021-11-26 20:00:47 -05:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
Tim Edwards be98da0fe6 Added spare logic block to caravel layout and verilog GL, wired 
it to the power supply, and checked top-level LVS.
 2021-11-24 16:50:22 -05:00
Tim Edwards 08a2c90940 Made updates to correct LVS errors in caravan. Found one major error in the RTL 
verilog for both caravel and caravan.  Hand-edited the RTL and GL netlists to
correct this;  still need to correct the layouts.  The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing.  Will route this by hand.
 2021-11-22 22:35:52 -05:00
Tim Edwards 515b5a54f2 Updates for LVS. Only LVS issue remaining for caravel is how to get the 
ground domains to extract independently.
 2021-11-22 12:00:55 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that 
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
 2021-11-21 22:58:39 -05:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00