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caravel
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303 Commits

Author SHA1 Message Date
Tim Edwards 1eb023d973 Added isolated substrate markers in mgmt_protect_hv, should fix the 
last of the LVS issues.
 2021-11-21 23:04:45 -05:00
Tim Edwards 6eb8bb54de Several more LVS corrections, including fixing a label in chip_io that 
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
 2021-11-21 22:58:39 -05:00
Tim Edwards 5262f35610 Modifications done as part of LVS on the caravel top level. 2021-11-21 22:07:16 -05:00
Tim Edwards 60bdc7e6a4 Moved some supply lines over in chip_io_alt for Caravan to make it 
more compatible with the routing that was copied over from Caravel.
 2021-11-21 13:00:44 -05:00
Tim Edwards d87d60cb9b Finished first draft of the caravel power routing (prior to LVS). 2021-11-21 12:41:46 -05:00
Tim Edwards 29dbc77591 More power routing, still a work in progress. 2021-11-20 22:53:18 -05:00
Tim Edwards 6570429234 Continued work on the power routing. Also updated the management 
core wrapper view with the LEF view from caravel_pico.
 2021-11-20 22:04:46 -05:00
Tim Edwards 8f75362f82 Start of power routing. 2021-11-20 18:04:43 -05:00
Tim Edwards b0d3217280 Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag 
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block).  Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there.  Reinstated the copyright, user ID text, open source
logo, and Caravel logo.  Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
 2021-11-20 13:43:49 -05:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 5cd3843f00 [DATA] Update gpio_control_block (li1 used 2um) 2021-11-20 14:43:20 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 866755f228 [DATA] Update mgmt_protect mag/gds to remove the shorted power nets 2021-11-19 15:50:36 +02:00
manarabdelaty bf6ad67934 [DATA] Update gpio_control_block pin order to fix shorts at the top level 2021-11-19 13:13:24 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
Tim Edwards 559675d392 Corrected chip_io and chip_io_alt layouts to restore the accidentally 
deleted "resetb_core_h" port label.  Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
 2021-11-15 17:13:43 -05:00
Tim Edwards f28950695d Made adjustments to the padframe routing to move all routes closer 
to the padframe and free up more space for routing in the chip
interior.
 2021-11-15 11:52:08 -05:00
Tim Edwards aefa72281c Added the files for the simple_por block design, and placed the latest 
hardened macro components into the caravel and caravan layouts.
 2021-11-15 10:34:52 -05:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 4c9f7630ff Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-15 13:24:42 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
Tim Edwards 67e48e53c5 Corrected minor DRC errors around the padframe cell and in the new 
caravan logo layout.  Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
 2021-11-12 16:12:12 -05:00
Tim Edwards 46dd9493f6 Removed some vestiges of top-level routing that were left over 
from the previous version of the caravel and caravan layouts.
 2021-11-12 13:45:58 -05:00
Tim Edwards d5ef31e391 Added an empty management core wrapper to the caravel top level. 2021-11-12 12:17:52 -05:00
Tim Edwards 27fdba364b Added user 1.8V power supply rails to the chip_io and chip_io_alt 
layouts.  Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell.  These
internal lines were previously in the power routing cells.
 2021-11-10 17:13:43 -05:00
Tim Edwards 38dbd8d5d9 Added logo graphic for Caravan. 2021-11-09 22:47:31 -05:00
Tim Edwards 8da7d5124b Added a logo for Caravel. 2021-11-09 17:18:20 -05:00
manarabdelaty 89bb33fbc0 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-11-08 13:35:16 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
Tim Edwards 27e0c94997 Added caravan top level and seeded with the GPIO control blocks, 
default blocks, and updated copyright.
 2021-11-06 22:34:49 -04:00
Tim Edwards cd906cbf8a Updated the copyright block for the new designs. Added caravel 
layout and placed the GPIO control blocks and default blocks.
 2021-11-06 22:13:19 -04:00
Tim Edwards 6a93ea582d Added a script which parses the file "user_defines.v" in 
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file.  Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
 2021-11-06 21:19:42 -04:00
Tim Edwards f53590d4b5 Split the layout of the GPIO defaults block into three versions, for the 
three parameterized values used in the RTL verilog.  Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
 2021-11-06 13:28:26 -04:00
Tim Edwards 33140b67a5 Edited the gpio_defaults_block layout like the user_id_programming 
cell to have landing sites for vias on both the HI and LO pins of
each conb_1 cell, in preparation for via programming.
 2021-11-06 12:59:49 -04:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 49c506f052 Update gpio_control_block after constrainting the clock period to be half the mgmt_core frequency 2021-11-05 18:36:43 +02:00
manarabdelaty e68664101c Update gpio_control_block 2021-11-05 16:54:55 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00
Tim Edwards ba932643e6 Changed the chip_io and chip_io_alt layouts to implement the 
continuous ring of vccd and vssd.  The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
 2021-11-03 15:57:46 -04:00
Tim Edwards 9fb3925649 Updated the OSHW (open source hardware) icon graphic layout, which was 
badly digitized, and not taking advantage of the allowance of 45 degree
angles on metal5.
 2021-11-01 17:25:34 -04:00
Tim Edwards dd66d1e5ca Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped" 
cell to the simpler (and easier to remember) "xres_buf".
 2021-10-31 21:43:09 -04:00
Tim Edwards 3a57940371 Revised the management protect block to include protections against 
an unconnected wishbone bus (unconnected inputs).  Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
 2021-10-27 19:36:43 -04:00
Tim Edwards a7148378a0 Added as many of the magic database layout files as are expected to remain 
unchanged between the caravel and caravel_openframe repositories.
 2021-10-26 10:27:03 -04:00