Commit Graph

5 Commits

Author SHA1 Message Date
Kareem Farid d14035d8a2 gpio_signal_buffering rtl decaps
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
2022-11-01 19:16:53 +02:00
Tim Edwards 69d353f65c Corrected the verilog and the layout for the caravan version of the
signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
Tim Edwards ac209d2397 Corrected a bunch of typos (different signal names used in the
same file), errors (buffer output pin name, power supplies not
passed at the top level).  Corrected a major error that prevented
the use of the buffers in simulation, so this was not previously
verified by simulation.  The buffering has now been properly
verified.
2022-10-14 10:51:29 -04:00
Tim Edwards f7ec0cd012 Added buffers to the top level, inside a macro called
gpio_signal_buffering (gpio_signal_buffering_alt in caravan).
Note that this macro requires manual placement and routing, like
the padframe, and the top level will need to route around its own
internal routes.
2022-10-13 13:29:27 -04:00