6570429234
Continued work on the power routing. Also updated the management
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core wrapper view with the LEF view from caravel_pico.
2021-11-20 22:04:46 -05:00
8f75362f82
Start of power routing.
2021-11-20 18:04:43 -05:00
b0d3217280
Replaced the gpio_defaults_block_0000.mag layout with gpio_defaults_block.mag
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so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
2021-11-20 13:43:49 -05:00
ededa9ed35
[DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core
2021-11-19 16:51:28 +02:00
2574eada93
[DATA] Add initial caravel layout
2021-11-19 01:37:10 +02:00
aefa72281c
Added the files for the simple_por block design, and placed the latest
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hardened macro components into the caravel and caravan layouts.
2021-11-15 10:34:52 -05:00
67e48e53c5
Corrected minor DRC errors around the padframe cell and in the new
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caravan logo layout. Current design is DRC clean with the new
open_pdks maglef views of the I/O cells.
2021-11-12 16:12:12 -05:00
46dd9493f6
Removed some vestiges of top-level routing that were left over
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from the previous version of the caravel and caravan layouts.
2021-11-12 13:45:58 -05:00
d5ef31e391
Added an empty management core wrapper to the caravel top level.
2021-11-12 12:17:52 -05:00
8da7d5124b
Added a logo for Caravel.
2021-11-09 17:18:20 -05:00
cd906cbf8a
Updated the copyright block for the new designs. Added caravel
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layout and placed the GPIO control blocks and default blocks.
2021-11-06 22:13:19 -04:00
Tim Edwards
manarabdelaty