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caravel
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1389 Commits

Author SHA1 Message Date
M0stafaRady b5fb97e5f4 rename run.py to cocotb.py 2022-10-02 04:22:44 -07:00
M0stafaRady 9e0be5473d remove hex files from directory 2022-10-02 04:20:32 -07:00
M0stafaRady 1c48f527b8 add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
M0stafaRady 199d5c0f5c fix bug assert csb before reset for the GL sim to work 2022-10-01 12:36:02 -07:00
M0stafaRady 53e868abdf add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
M0stafaRady d12fac2ad1 update run script to delete vcs files before test run 2022-10-01 12:28:52 -07:00
Mohamed Shalan d93db4d259
Merge pull request #131 from efabless/fix_pwr_ctrl_reset_value 
Added reset values for pwr_ctrl_out in housekeeping
 2022-10-01 19:20:33 +02:00
M0stafaRady 555488c832 fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00
M0stafaRady 9615629a42 fix bug bit time calculation 2022-10-01 02:53:24 -07:00
M0stafaRady 68c88b116a increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
M0stafaRady 18b4f36525 add test uart_rx 2022-10-01 02:23:47 -07:00
M0stafaRady 407b0be306 Update script to return fatal error when hex generation fails 2022-10-01 01:48:55 -07:00
M0stafaRady f2ca45358b remove AN.DB folder from git hub 2022-09-30 03:52:34 -07:00
M0stafaRady 7546ce10c7 simple readme 2022-09-30 03:52:34 -07:00
M0stafaRady f08c22023c Apply automatic changes to Manifest and README.rst 2022-09-30 03:52:34 -07:00
M0stafaRady f8c8d831d0 Add RTL for 2 debug regs used to test and located inside user_project_wrapper 2022-09-30 03:52:34 -07:00
M0stafaRady fc8369443c fix bug move some housekeeping initialization wires and regs before they are used 2022-09-30 03:52:34 -07:00
M0stafaRady add4c5f6c8 Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
RTimothyEdwards b1208adfc6 Apply automatic changes to Manifest and README.rst 2022-09-29 18:11:39 +00:00
R. Timothy Edwards f07958d4ec
Merge branch 'caravel_redesign' into fix_pwr_ctrl_reset_value 2022-09-29 14:10:41 -04:00
Marwan Abbas c9c7fc5533
Merge pull request #134 from efabless/fix_user_pass_thru 
Fix user pass thru
 2022-09-29 19:52:13 +02:00
PriyankaDilip ec9fe7939f
Error in User Area Base Address (#97) 2022-09-29 07:14:41 -07:00
R. Timothy Edwards c363d52ccc
Corrected the documented solder bump dimension in the diagram (#133) 
die_pads.svg from 250um to 350um diameter.
 2022-09-29 07:10:53 -07:00
kareem 7c524edd31 openlane(wip)!: housekeeping 
~ fix typo in referencing variables in sdc file
~ fine tune parameters to get the design to route
with cts and diode insertion

!important:
depends on SAVE_LIB patch from openlane
 2022-09-29 05:30:03 -07:00
Kareem Farid 0a56c1c4eb update housekeeping sdc 2022-09-29 12:54:28 +02:00
RTimothyEdwards 52d2b94e81 Apply automatic changes to Manifest and README.rst 2022-09-28 19:39:43 +00:00
Tim Edwards dd6088e013 Corrected the instance name of the topmost GPIO defaults block on 
the left hand side of caravan from gpio_defaults_block_14 to
gpio_defaults_block_25.  Otherwise, the script that generates the
custom user configuration won't be able to change the defaults
for GPIO 25.
 2022-09-28 15:36:24 -04:00
kareem 53950bb206 openlane: update gpio_control_block config 
- point to the right template file
- add skiptrim flag
 2022-09-28 01:03:00 -07:00
RTimothyEdwards 170f5aa102 Apply automatic changes to Manifest and README.rst 2022-09-28 01:01:11 +00:00
Tim Edwards aba145e0e2 Made modifications in support of changing the hard-coded default 
configuration of GPIO 3 (CSB) from a standard input to a weak
pull-up input.
 2022-09-27 20:58:57 -04:00
RTimothyEdwards 586f5051e3 Apply automatic changes to Manifest and README.rst 2022-09-27 15:32:19 +00:00
Tim Edwards 65553a5af3 Added reset values for pwr_ctrl_out in housekeeping (fixes caravel 
github issue #106).
 2022-09-27 11:30:02 -04:00
kareem acf92c3460 views: update gpio_control_block gds 2022-09-27 07:42:32 -07:00
kareem 85f7f86c4e reharden!: gpio_control_block 
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
 2022-09-27 07:09:26 -07:00
jeffdi e3b2cd9458 Apply automatic changes to Manifest and README.rst 2022-09-21 17:37:17 +00:00
Jeff DiCorpo 6137a23e01
Merge branch 'caravel_stanford' into fix_direct_power_connections 2022-09-21 10:36:19 -07:00
Jeff DiCorpo 74a9f24476
Update Makefile 
update open_pdks commit id
 2022-09-21 10:25:30 -07:00
jeffdi baeb1cc551 add log for verify simulation output 2022-09-20 18:27:21 -07:00
jeffdi d8399ae6f5 add log for verify simulation output 2022-09-20 18:12:58 -07:00
jeffdi 3fd3107cae add log for verify simulation output 2022-09-20 17:44:50 -07:00
jeffdi 85847dfe05 update for dv simulations for mgmt core 2022-09-20 16:49:20 -07:00
jeffdi a04966d62d update for dv simulations for mgmt core 2022-09-20 16:36:00 -07:00
jeffdi fdbe225674 update for dv simulations for mgmt core 2022-09-20 15:31:51 -07:00
RTimothyEdwards 19a7b303e9 Apply automatic changes to Manifest and README.rst 2022-09-20 22:25:10 +00:00
Tim Edwards 2606285b8c Flipped some lines where a wire was used before it was declared. 2022-09-20 18:23:32 -04:00
RTimothyEdwards b9a819634d Apply automatic changes to Manifest and README.rst 2022-09-20 21:56:37 +00:00
Tim Edwards c7d01796bd Merge branch 'fix_direct_power_connections' of https://github.com/efabless/caravel into fix_direct_power_connections 
Pulling from remote
 2022-09-20 17:55:02 -04:00
Tim Edwards 66fc0c6a06 Modified the GPIO control block to buffer the constant high/low outputs. 
Corrected the pad constant connections to all be in the correct domain
(1.8V or 3.3V).  Created a new "constant_block" module that generates
a single constant 1 and 0 value in the 1.8V domain, and used 7 of these
in the chip_io (and chip_io_alt) modules to create the 1.8V domain
constant signals for the seven pads belonging to the management (clock,
reset, flash SPI, and management GPIO).
 2022-09-20 17:49:08 -04:00
jeffdi 4a4c346bf6 Merge remote-tracking branch 'origin/caravel_stanford' into caravel_stanford 2022-09-20 14:41:52 -07:00
jeffdi 3f3c3db099 update for dv simulations for mgmt core 2022-09-20 14:41:43 -07:00