4 Commits

Author	SHA1	Message	Date
M0stafaRady	650483eaa2	fix some typos on mgmt_protect	2022-10-05 03:27:46 -07:00
Tim Edwards	de9605a01b	Modified the mgmt_protect module to change the tristate outputs to ... zero level outputs when the user project area is powered down. That allows the synthesis tools to buffer these outputs. The protection from floating inputs is left as-is, but all logic that was unnecessary to be specified by gate instances has been changed to RTL. This leaves only a handful of signals (logic analyzer input, user IRQ, and wishbone data out and acknowledge out) to be handled by explicit logic gate instances.	2022-10-03 16:11:02 -04:00
Tim Edwards	3a57940371	Revised the management protect block to include protections against ... an unconnected wishbone bus (unconnected inputs). Added the missing signals for the user IRQ enables to management protect (which have to come from the management SoC).	2021-10-27 19:36:43 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00