6bed433856
One additional small change to the signal buffer layouts to avoid
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a collision with the lower three right-hand side I/O cells that
was discovered by LVS.
2022-10-17 15:51:43 -04:00
69d353f65c
Corrected the verilog and the layout for the caravan version of the
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signal buffering (verilog was missing one of the buffers, and the
layout had some of the labels at the top accidentally erased).
2022-10-16 21:06:27 -04:00
48ae31205c
Another change to the pin endpoint positions to make sure that they
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have at least 0.28um spacing to the next wire. Not sure that this
is going to solve the router errors, though.
2022-10-16 14:15:12 -04:00
c5e7c67d60
Once again. . . Rewrote the RTL verilog so that only signals
...
being buffered pass through the buffer macros. Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
589f351dcb
Additional modification to move pins up into an uncongested area
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above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections. Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
a77a45babe
Adjustments to the top level buffering cells to do various things
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like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
3db846b119
Fixes issues with the GPIO signal buffering by applying a bounding
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box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
92e2f5e8a4
Added layout views (.mag, GDS, DEF, and LEF) for the caravan
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variant of the top level GPIO signal buffering (module
gpio_signal_buffering_alt).
2022-10-14 16:06:11 -04:00
Tim Edwards