caravel

Commit Graph

Author	SHA1	Message	Date
Tim Edwards	6eb8bb54de	Several more LVS corrections, including fixing a label in chip_io that got removed from its net by a chang in the LEF view of an I/O pad, and a lack of declaration of an array to attach to pwr_ctrl_out in the verilog, which is valid verilog but netgen can't know the bus size without the no-connect net being declared. The remaining issue has to do with separation of ground domains in the mgmt_protect block.	2021-11-21 22:58:39 -05:00
Tim Edwards	aefa72281c	Added the files for the simple_por block design, and placed the latest hardened macro components into the caravel and caravan layouts.	2021-11-15 10:34:52 -05:00

Author

SHA1

Message

Date

Tim Edwards

6eb8bb54de

Several more LVS corrections, including fixing a label in chip_io that

got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared.  The remaining issue has to
do with separation of ground domains in the mgmt_protect block.

2021-11-21 22:58:39 -05:00

Tim Edwards

aefa72281c

Added the files for the simple_por block design, and placed the latest

hardened macro components into the caravel and caravan layouts.

2021-11-15 10:34:52 -05:00

2 Commits