to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping). The two housekeeping tests fail and need to be
debugged.
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
since the original one was folded into the sysctrl testbench, but that
testbench no longer uses the SPI master. Moved the SPI master from being
an overlay of the housekeeping SPI to occupying GPIO pins 32 to 35.
Made GPIO 35 a bidirectional pin like 36 and 37 so that the output enable
from the SPI master can be used.
storage. Not all of these pass simulation checks. Added back the
bit-bang control of the GPIO programming. Added back the read-only
interface between the housekeeping module and the SRAM 2nd port.
Revised the memory map text document to reflect the addition of the
SRAM ports. There is not yet a testbench for the SRAM read-only
interface.
the 26 domain (now dedicated to the housekeeping module), with
2e0... now 261... and 2f0... now 262... Although this is not
strictly backwards-compatible, the addresses in defs.h have been
modified so that C code remains valid with a recompile.
Tim Edwards