to resolve the problem with the typo that caused the propagated
GPIO serial load, reset, and clock signals to get scrambled on the
user2 side. Caravel is now LVS clean again (Caravan needs layout
work).
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
Fixed rstb_h, which was being input to low-voltage blocks. (2)
Fixed flash_csb_ieb_core and flash_clk_ieb_core, which were not
output from housekeeping as they should be; the solution was
to tie the INP_DIS lines low at the pad by connecting them to
the TIE_LO_ESD line. This should probably be addressed in
housekeeping but would change the current pinout.
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
so that it contains a valid layout after processing by Openlane (since the
verilog module is named gpio_defaults_block). Corrected the orientation of
the defaults block layouts on the right side of Caravel and erased the
incorrect routing there. Reinstated the copyright, user ID text, open source
logo, and Caravel logo. Revised the gen_gpio_defaults.py script to handle
the first five GPIOs in the same way as the others, although as fixed entries
which cannot be modified by the user project designer.
deleted "resetb_core_h" port label. Corrected the chip_io and chip_io_alt
verilog RTL files to replace the user area power supply clamp cells with
the new clamped3 cell from open_pdks.
layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
Tim Edwards
manarabdelaty