riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
216 Commits 140 Branches 61 Tags 15 GiB
Commit Graph

1 Commits

Author SHA1 Message Date
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing 
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
 2021-12-07 10:06:35 -05:00