~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys
!need to verify that the oscillator remains untouched
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo
!important same work arounds as before
~ update interactive script for chip_io.v for recent openlane
~ update config.tcl for recent openlane
~ add a verilog stub for sky130_fd_io__top_xres4v2 as
the io verilog models are not readable by yosys
- reimplement using a sparecell
- reimplement using newest open_pdks
!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible
!important override abstract lef generated by openlane. openlane
generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds
!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations
!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
~ fix typo in referencing variables in sdc file
~ fine tune parameters to get the design to route
with cts and diode insertion
!important:
depends on SAVE_LIB patch from openlane
Mohamed Shalan
mo-hosni
kareem
marwaneltoukhy
Marwan Abbas
Passant
Mohamed Hosni