3 Commits

Author	SHA1	Message	Date
kareem	bb2d983e03	+ add a size 16 buf for clockp signal in digital_pll	2022-10-13 05:57:09 -07:00
jeffdi	619163aec1	fixes for RTL testbenches with mgmt core wrapper	2021-12-05 10:11:10 -08:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00