Commit Graph

6 Commits

Author SHA1 Message Date
Tim Edwards c5e7c67d60 Once again. . . Rewrote the RTL verilog so that only signals
being buffered pass through the buffer macros.  Removed the
straight-through signals from the layout, and renumbered the
vectors in the buffer cells, which no longer match the numbering
at the top level (unfortunately).
2022-10-16 12:49:44 -04:00
Tim Edwards 589f351dcb Additional modification to move pins up into an uncongested area
above housekeeping, because the upper GPIO pins are in the wrong
place relative to the new GPIO signal routing below the SoC.
Added pins for the pass-through connections.  Unconnected/
unrouted OEB pins are still not present and probably should be
removed from the RTL.
2022-10-16 10:52:53 -04:00
Tim Edwards dcc3c56b83 Some additional corrections to the gpio_signal_buffering cells.
Corrected one instance where a buffer had incorrectly been replaced
with a decap cell.  Moved the left-hand side in by 0.6um to clear
the chip_io connections on the left-hand side.  Corrected a small
DRC error in a route position at the bottom.
2022-10-16 09:50:20 -04:00
Tim Edwards a77a45babe Adjustments to the top level buffering cells to do various things
like avoid obstructions in the padframe and power routing, add
decap, and separate coupling wires to reduce capacitance.
2022-10-15 17:35:17 -04:00
Tim Edwards 3db846b119 Fixes issues with the GPIO signal buffering by applying a bounding
box to the layout, so that LEF and DEF positions are correct.
2022-10-15 10:31:35 -04:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS,
LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00