52 Commits

Author	SHA1	Message	Date
Tim Edwards	bdfa747145	First major update; current code passes syntax checks in iverilog ... and simulates, but fails testbench (not surprising at this stage).	2021-10-15 21:49:49 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00