3 Commits

Author	SHA1	Message	Date
Tim Edwards	e6a94449ce	Modified the housekeeping SPI to generate a read strobe (or rather ... status) so that between rdstb and wrstb, the SPI signals when it is about to read or write a byte. The back-door wishbone interface then stalls the CPU during these periods. That allows the CPU to continue running while the SPI is being accessed without data collisions and without having to stall for the entire time CSB is held low. Because SCK is asynchronous to the clock, rare collisions are still possible; this is not expected to be an issue but might be worth investigating.	2021-10-23 22:06:24 -04:00
Tim Edwards	bdfa747145	First major update; current code passes syntax checks in iverilog ... and simulates, but fails testbench (not surprising at this stage).	2021-10-15 21:49:49 -04:00
Tim Edwards	332f9ec2e7	Seeding with documentation of pinout and verilog RTL (mostly unchanged ... from original except to remove blocks that are not supposed to be in this repository like the processor core and the storage).	2021-10-12 16:31:42 -04:00