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465 Commits

Author SHA1 Message Date
RTimothyEdwards b553b39f5f Apply automatic changes to Manifest and README.rst 2021-12-24 16:48:26 +00:00
Tim Edwards 55836db2d2 Added a reference to the new file "gl/mgmt_defines.v" in the 
caravel_pico repository.  The issue is that each SoC implementation
defines its own modules and therefore needs its own includes.  The
implication is that this file now needs to exist in every SoC
implementation's verilog/gl/ directory.
 2021-12-24 11:46:34 -05:00
Tim Edwards 28931e7968 Added more documentation, fully documenting the GPIO, and various 
aspects of the memory mapped controls for the management protection,
and the various differences between the Caravel and Caravan chips.
 2021-12-23 11:54:36 -05:00
Marwan Abbas 0792dc6930
Create memory_map.rst 2021-12-23 14:41:53 +02:00
Marwan Abbas 56110e66e8
Create gpio_configuration.rst 2021-12-23 14:12:48 +02:00
Marwan Abbas 027dfe8d23
Create clamp_list.rst 2021-12-23 13:53:12 +02:00
Marwan Abbas 070e178c31
Update digital_locked_loop.rst 2021-12-23 13:38:01 +02:00
Marwan Abbas 7d3a8de7b9
Create digital_locked_loop.rst 2021-12-23 12:25:41 +02:00
Jeff DiCorpo 4189166cc9
Update Makefile 
update OPEN_PDKS_COMMIT to 1.0.255
 2021-12-22 12:05:09 -08:00
Jeff DiCorpo 6b61d51f8b
Merge pull request #1 from Manarabdelaty/update_spice 
Update spice netlists to include power routing
 2021-12-22 09:20:16 -08:00
Tim Edwards 31e3d9c106 Started a set of text documents to describe all of the register sets 
and describe the various functions of Caravel (especially housekeeping).
This should eventually be formatted to match the rest of the
documentation.
 2021-12-21 20:00:29 -05:00
manarabdelaty ee0950fdb9 Update spice netlists to include power routing 2021-12-21 19:34:43 +02:00
jeffdi 1c9ca7e693 correct path for image in docs 2021-12-19 09:47:30 -08:00
Tim Edwards 5f563c3f4f Corrected a statement in the LVS scripts in the mag/ directory that 
is Makefile syntax, not bash syntax, and will cause the script to
produce an incorrect LVS result without generating a syntax error.
 2021-12-17 22:27:32 -05:00
jeffdi dd71e938ce Apply automatic changes to Manifest and README.rst 2021-12-17 19:58:20 +00:00
jeffdi c50fff8e3b Merge remote-tracking branch 'origin/main' into main 2021-12-17 11:57:20 -08:00
jeffdi ee7eded766 add documentation 2021-12-17 11:55:08 -08:00
jeffdi 5b1d99f934 Apply automatic changes to Manifest and README.rst 2021-12-17 01:51:53 +00:00
jeffdi e5cf492e0a add documentation 2021-12-16 17:51:16 -08:00
jeffdi 3ccce01467 add documentation 2021-12-16 17:41:16 -08:00
Tim Edwards ccd0a19af7 Organized the documentation, corrected and extended the entries. The original 
datasheet has been broken up into individual pages;  these can be recast into
sphinx or HTML as needed, while the graphics have been exported to SVG.
 2021-12-16 17:32:38 -05:00
Jeff DiCorpo 6f80be7ea8 add manifest 2021-12-16 14:26:20 -08:00
Jeff DiCorpo f58ab21244
Update Makefile 2021-12-16 14:08:34 -08:00
jeffdi 482c6a3ff8 Merge remote-tracking branch 'origin/main' into main 2021-12-16 13:56:45 -08:00
jeffdi 8907a3d239 adding user_project_wrapper empty files -- gds & lef 2021-12-16 13:56:36 -08:00
Jeff DiCorpo 2776c9e030
Update auto-update-caravel-lite.yml 2021-12-16 13:52:04 -08:00
jeffdi 2bc184f5c1 Merge remote-tracking branch 'origin/main' into main 2021-12-16 12:29:44 -08:00
jeffdi d4e6ed5684 adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
manarabdelaty e60957d73b [DATA] Update sdf for chip_io to include pad delays 2021-12-16 15:58:58 +02:00
manarabdelaty a04d2b4a35 Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-16 15:25:28 +02:00
manarabdelaty e03fd0ecaf Update sdf files to have the temp value at the typical corner to avoid having cvc complaint about it 2021-12-16 15:25:08 +02:00
Jeff DiCorpo d825da37bb
Create LICENSE 2021-12-15 23:53:39 -08:00
Jeff DiCorpo d35d898477
Delete info.yaml 2021-12-15 23:42:45 -08:00
Jeff DiCorpo c08f6f5a85
Update auto-update-caravel-lite.yml 2021-12-15 23:38:04 -08:00
Jeff DiCorpo b4f0140f83
Update auto-update-caravel-lite.yml 2021-12-15 23:30:37 -08:00
Jeff DiCorpo 1775a9bffc
Update auto-update-caravel-lite.yml 2021-12-15 23:25:13 -08:00
Jeff DiCorpo 67fa1f26eb
Update auto-update-caravel-lite.yml 
adds EFSTAFF_TOKEN instead of ssh token
 2021-12-15 22:03:29 -08:00
Jeff DiCorpo a8023fa349
Create auto-update-caravel-lite.yml 2021-12-15 20:20:37 -08:00
manarabdelaty a55129af5f Update sdf file divider 2021-12-14 14:30:00 +02:00
manarabdelaty fa374d7d6c Merge branch 'main' of https://github.com/efabless/caravel_openframe into main 2021-12-09 22:16:00 +02:00
manarabdelaty 92f1ab7ace [DATA] Update chip_io_alt.gds to match the mag view 2021-12-09 22:15:05 +02:00
Tim Edwards ec93c72d18 Modified simple_por.v RTL to avoid the wire declaration that "cvc" 
doesn't like (even though it's perfectly legal).
 2021-12-08 12:16:19 -05:00
Tim Edwards b9fdac94ff Corrected a typo in the run_chip_io_alt_lvs.sh script. 2021-12-08 10:06:50 -05:00
Tim Edwards 75f4e49a99 Removed two floating metal2 rectangles from chip_io_alt. 2021-12-08 10:00:57 -05:00
manarabdelaty 2aa61e7bff [DATA] Update gpio_control_block gds to match the mag view 
- now has the substrate cut layer for isolating the two ground domains and passes LVS on the gds
 2021-12-08 15:14:04 +02:00
Tim Edwards 8cac89ec74 Changed the user project wrapper and user analog project wrapper 
to be abstract views, and modified the LVS scripts accordingly
(they no longer need a special version of the netgen setup
script).  LVS was verified on both caravel and caravan using this
setup.
 2021-12-07 22:21:49 -05:00
Tim Edwards 489bddcf98 Two more changes: (1) Correction to chip_io_alt.v RTL verilog to 
match what was done earlier on chip_io.v, and (2) Corrected a
set of four labels in chip_io_alt.mag which had been rotated,
causing an error in LVS.
 2021-12-07 17:16:44 -05:00
Tim Edwards 624317bc3f Corrected the missing port designation on porb_h in chip_io.mag 
and chip_io_alt.mag.
 2021-12-07 12:38:18 -05:00
Tim Edwards 79828c00b3 Revised the LVS run scripts to use $PDK_ROOT instead of a hard- 
coded path.
 2021-12-07 10:32:22 -05:00
Tim Edwards c3fc004072 Corrected an error in verilog/gl/chip_io_alt.v, which was missing 
connections to the core side VCCD1 and VSSD1 on the clamped3 pads.
Also added scripts for running LVS on chip_io to the mag/ directory,
and revised the scripts so that they will only re-run extraction if
there is no netlist file in the mag/ directory.
 2021-12-07 10:06:35 -05:00