mo-hosni
77669e899e
reharden `caravel_clocking`.
2023-03-26 02:40:56 -07:00
mo-hosni
86612d1f08
reharden caravel_clocking.
2023-02-27 10:26:19 -08:00
kareem
3bd586b50c
reharden: caravel_clocking
...
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
2022-10-18 06:18:30 -07:00
kareem
3e3bd111c1
~ correct paths refereces in mag and maglef files from openlane
2022-10-15 04:06:07 -07:00
kareem
aadfb57609
reharden: caravel_clocking
...
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
kareem
c922241c3f
reharden: caravel_clocking
...
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
2022-10-13 10:54:04 -07:00
manarabdelaty
bd88221d17
[DATA] Update caravel_clocking
2021-12-07 13:36:56 +02:00
manarabdelaty
aa766f9144
[DATA] Update caravel_clocking module
2021-12-05 19:44:28 +02:00
manarabdelaty
ef1019b62a
[DATA] Update caravel_clocking
2021-12-02 22:50:20 +02:00
manarabdelaty
0067bd5b7c
[DATA] Update caravel_clocking/digital_pll/housekeeping
2021-12-02 21:09:43 +02:00
Tim Edwards
f67f7b6daf
Corrected bad paths on two layouts in mag/ and most of the layouts
...
in maglef/, all of which were erroneously pointing to paths in
either OpenLane or the user's home directory path.
2021-11-26 20:00:47 -05:00
manarabdelaty
8b1c5df909
[DATA] Update caravel_clocking module (timing clean)
2021-11-25 15:23:01 +02:00
manarabdelaty
37fb2d6766
[DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1)
2021-11-20 13:07:23 +02:00
manarabdelaty
64bdd6230d
[DATA] Update caravel_clocking module floorplan
2021-11-19 01:26:29 +02:00
manarabdelaty
72b2c724c9
[DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz
2021-11-15 15:50:43 +02:00