cells are replaced with the base cells. Routing to pins
is instead done in the "gpio_connects" cells while
improving on the original routing (fewer cross-overs,
multiple vias per contact, wider buses for the analog
signals). Made small adjustments to many of the openframe
wrapper pins to keep them all on a 10nm grid. Moved the
connections previously from the "wrapped" GPIO cell back
from the openframe project border, so that the border can
be clear of all blockages. Added the DEF file of the
wrapper (previously only in the openframe example repo)
to the def/ directory. Note: The modified LVS scripts
depend on the gate-level netlists of the frame, which
have been committed in a prior pull request. This pull
request does not conflict with those files.
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
view pointing to the contents of ../gds/ so that when the assembled
chip's GDS is generated with "cif *hier write disable", the POR
will continue to have the GDS with the proper hierarchical processing.
verilog for both caravel and caravan. Hand-edited the RTL and GL netlists to
correct this; still need to correct the layouts. The error causes the user1
side clock, load, and reset buffers to drive the user2 side as well as the user1
side, making a huge mess of the routing. Will route this by hand.
got removed from its net by a chang in the LEF view of an I/O pad, and
a lack of declaration of an array to attach to pwr_ctrl_out in the
verilog, which is valid verilog but netgen can't know the bus size
without the no-connect net being declared. The remaining issue has to
do with separation of ground domains in the mgmt_protect block.
Tim Edwards
mo-hosni
Kareem Farid