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252 Commits

Author SHA1 Message Date
M0stafaRady a572a8ec14 add gpio_all_i_user test 2022-10-10 09:07:32 -07:00
M0stafaRady e2245ad333 enhance gpio_all_i test to include more checkers 2022-10-10 07:42:02 -07:00
M0stafaRady 71d53b9958 added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list 2022-10-10 06:23:47 -07:00
M0stafaRady 0f0a495906 merge with caravel_redesign 2022-10-10 05:04:44 -07:00
M0stafaRady 688429eeda move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
M0stafaRady 45a885caaa update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT 2022-10-10 04:34:26 -07:00
M0stafaRady 00364eb092 Add gpio_all_o_user test 2022-10-09 07:53:25 -07:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
M0stafaRady 1690c8e068 enhance gpio_all_o test 2022-10-09 06:07:19 -07:00
M0stafaRady 08229d6a9b Add gpio_all_bidir test but it still not working yet 2022-10-09 05:08:12 -07:00
mo-hosni dde6e034e0 added constant_block view 2022-10-08 12:05:53 -07:00
Tim Edwards d1a3922dbb Initial commit for rework of chip_io and chip_io_alt layouts; 
includes RTL change inside the padframe definition to remove one
previously unnoticed hard-wired connection between VDDIO and a
3.3V domain digital input pin.
 2022-10-08 12:05:10 -04:00
M0stafaRady e94a8e0477 add test la test 2022-10-08 06:25:26 -07:00
M0stafaRady d90001eac2 update caravel.py to disable bin 3 also 2022-10-08 01:56:41 -07:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
R. Timothy Edwards 7b271a7808
Effectively reverted the change to add spare logic blocks near each (#157) 
* Effectively reverted the change to add spare logic blocks near each
of the GPIO control blocks by changing the definition of
NUM_SPARE_BLOCKS to 4 (the original number of spare logic blocks)
for both caravel and caravan top level RTL verilog modules.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
 2022-10-07 09:28:13 -07:00
M0stafaRady 2dc29bb207 comment disabling the housekeeping at the begining of each test as it's not needed anymore 2022-10-07 07:02:58 -07:00
M0stafaRady 0f167fc041 update timeout for gpio_all_i_pd and gpio_all_i_pu 2022-10-07 07:02:09 -07:00
M0stafaRady f072e9cb2d Add gpio_all_i_pd 2022-10-07 06:41:21 -07:00
M0stafaRady 6f832589c0 merge caravel_redesign 2022-10-07 06:06:14 -07:00
M0stafaRady e1eba1d534 update gpio_all_i_pu test 2022-10-07 06:04:18 -07:00
kareem 6d1d618974 reharden!: gpio_control_block 
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
 2022-10-07 05:02:14 -07:00
Jeff DiCorpo 0e3badac29
152 add pass thru for clock and reset (#154) 
* update caravel.v and caravan.v for clock and reset passthru.

* Apply automatic changes to Manifest and README.rst

* Apply automatic changes to Manifest and README.rst

Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu>
Co-authored-by: shalan <shalan@users.noreply.github.com>
 2022-10-07 01:36:26 -07:00
R. Timothy Edwards cfbe353290
Added spare logic blocks for GPIO (#153) 
* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-10-07 01:24:01 -07:00
R. Timothy Edwards be25ae7476
Remove SRAM read-only interface (#151) 
* Removed the SRAM read-only interface by wrapping all related code
in an ifdef for "USE_SRAM_RO_INTERFACE", which is undefined.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
 2022-10-07 01:23:07 -07:00
Tim Edwards a07d0d5dac Fixed one small error in the housekeeping module that was surfaced 
by the pull-up/pull-down testbench.
 2022-10-06 15:57:45 -04:00
M0stafaRady 3eb0b11380 update verify_cocotb.py to remove vcs generate files 2022-10-06 11:18:48 -07:00
M0stafaRady 4f483adb36 update hk_regs_wr_wb_cpu test to include all house keeping regs 2022-10-06 11:16:07 -07:00
M0stafaRady 7e407e1155 Add test hk_disable 2022-10-06 10:12:12 -07:00
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
R. Timothy Edwards 611c320eed
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-06 11:39:22 -04:00
M0stafaRady fb34d9a541 update input tests to cover the gpio from 32 to 37 2022-10-06 05:32:46 -07:00
M0stafaRady a69185dfca update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00
M0stafaRady 1bc78c4eea update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:43:02 -07:00
M0stafaRady 8e72d5e13e Add test uart_loopback 2022-10-06 03:12:44 -07:00
M0stafaRady 6830c79ae8 fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
Tim Edwards 42805f767e Removed some references to mgmt_soc_litex files that had been added 
to caravel_netlists.v when attempting to determine if the
verification testbenches could be run from caravel referencing
caravel_mgmt_soc_litex instead of the other way around.  This file
has been reverted back to its original form.
 2022-10-05 21:43:29 -04:00
Tim Edwards e2556cc11b Removed the SPARE_LOGIC_BLOCK ifdef...endif from around the spare 
logic in caravel.v and caravan.v.  These had been added to the
caravel_stanford branch because the spare logic blocks are not
usefully synthesizable.
 2022-10-05 21:37:55 -04:00
R. Timothy Edwards 268f5dd7e9
Merge branch 'caravel_redesign' into fix_direct_power_connections 2022-10-05 21:33:17 -04:00
Tim Edwards 83f58cbe65 Added back a "genvar" statement that was deleted from housekeeping 
along with an unused block, but was needed elsewhere.
 2022-10-05 21:05:58 -04:00
Tim Edwards 72341326e2 Corrected a typo in the definition of the mgmt_io_oeb vector in 
caravel.v, which should be the same as mgmt_io_in and mgmt_io_out
and should equal the number of user I/O pads (38).
 2022-10-05 20:52:21 -04:00
Tim Edwards f5a9d4677e Revert "Implemented fix from early issue #16. Finally decided to pull the" 
This reverts commit 577cc12fe0.

Reverting the change from issue #16.  After some discussion, it has
been decided that it is up to the user to implement the pull-up and
pull-down modes correctly by setting the output enable and driving
the output to the appropriate value.  Note that this should be well
documented, if by nothing else than a validation testbench that
excercises a user pull-up and pull-down input mode.
 2022-10-05 20:46:03 -04:00
M0stafaRady a6e7b46128 delete reading from uart register in uart_rx test 2022-10-05 15:07:38 -07:00
M0stafaRady 78613c95cc increase timeout for uart_rx and add uart_ev_pending_write 2022-10-05 15:02:07 -07:00
M0stafaRady 8e21a2f722 Add test pll 2022-10-05 13:58:36 -07:00
M0stafaRady b31efbdeea IO[0] affects the uart selecting btw system and debug 2022-10-05 13:47:23 -07:00
mo-hosni 9c850bf94b rehardened housekeeping 2022-10-05 12:35:03 -07:00
mo-hosni fcc009e65a rehardeneded mgmt_protect 2022-10-05 12:26:24 -07:00
Tim Edwards 577cc12fe0 Implemented fix from early issue #16. Finally decided to pull the 
trigger on this one in the hopes that it helps prevent user error
in implementing input pull-up and pull-down on GPIO pins.
 2022-10-05 14:13:57 -04:00