layouts. Because the 1.8V domains are no longer within the pad
ring buses, they need to be connected together in the cell. These
internal lines were previously in the power routing cells.
makes backup copies of caravel and caravan layouts and replaces the
cell name of any gpio defaults block that is changed from the
contents of user_defines.v. NOTE: user_defines.v ultimately must
reside in the user project. The Makefile should copy the user's
version into the caravel directory space before running the script,
or else the script should be rewritten to reference the user's
project area when reading user_defines.v.
verilog/rtl/, and creates all the layout files needed to represent
all unique combinations of defaults used in the file. Not done:
Modifying the top level layout to use the correct defaults (because
the top level layout does not yet exist).
three parameterized values used in the RTL verilog. Modified the
"user_defines.v" file to create verilog definitions that match the C-style
definitions from "defs.h", for convenience/simplicity.
fixed by moving from after the managment protect to before it, but
an inversion of the signal was missed, leading to an incorrect
wb_rst_i passed to housekeeping. (2) Revised the method to load
the serial GPIO data chain from a 2-pin, I2C-like method to a
more straightforward 3-pin method with separate reset, clock, and
load pins. The load pin propagates through the chaing like the
other two. Added a bit-bang signal for the load signal as well.
(3) Added an implied buffer after the data output of the GPIO
control block to ensure that the data arrives at the next control
block after the clock, to prevent hold violations.
continuous ring of vccd and vssd. The clamp connections for the
vccd1/vssd1 and vccd2/vssd2 pads still need to be done, although
the pads themselves have been changed to the base cell, matching
the new verilog RTL.
incorrectly assigned to the clock on the user side of the managment
protect block, causing it to be undefined when the user area power
supply is down. The "hkspi_power" testbench which tests using the
housekeeping SPI while the user area power is grounded now works
correctly.
around the entire padframe. The vccd1 and vccd2 domains are local
to their respective pads, and any bus routing must be done inside
the padframe. This means that all pads operate on global vddio for
3.3V as before, but also global vccd for 1.8V. The user 1.8V voltage
domain only goes as far as the input to the GPIO control block.
to areas not part of the management SoC, including chip_io,
mgmt_protect, and mprj_ctrl and sysctrl_wb (which are now part of
housekeeping). The two housekeeping tests fail and need to be
debugged.
management SoC to the management protect block, and updated the
documentation to include the new wishbone interface for those
signals, and the additional signals on the management SoC pinout.
an unconnected wishbone bus (unconnected inputs). Added the missing
signals for the user IRQ enables to management protect (which have
to come from the management SoC).
implement the arbitration between SPI and back-door. The back-door
access flags when it is going to do a read or write, and the SPI
can have an invalid read or fail a write if the SPI is too fast,
but the wishbone access should be valid. As long as the SPI is
much slower than the core clock (say, 1MHz) then there should be no
contention, which means that contention can always be avoided simply
by slowing the SPI signaling down.
status) so that between rdstb and wrstb, the SPI signals when it is
about to read or write a byte. The back-door wishbone interface then
stalls the CPU during these periods. That allows the CPU to continue
running while the SPI is being accessed without data collisions and
without having to stall for the entire time CSB is held low.
Because SCK is asynchronous to the clock, rare collisions are still
possible; this is not expected to be an issue but might be worth
investigating.
manarabdelaty
Tim Edwards