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caravel
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185 Commits

Author SHA1 Message Date
D. Mitch Bailey 999d5e2311 Fixed verilog instance name and ports. 2024-09-01 08:23:15 -07:00
David Lindley d53ed92620 Updated mag files by swapping decap_12 cells with fill_4 and fill_8. Modified the verilog/gl files to match. 2024-08-29 17:22:17 -07:00
Tim Edwards 4cd9d9cf2a Added pins "vddio" and "vssio" to the openframe and openframe project 
wrapper RTL netlists and and openframe project wrapper GL netlist.
 2023-10-18 12:47:56 -04:00
Tim Edwards 7bfab382d8 After updating from the PR that adds the gate level chip_io_openframe.v, 
modified it so that it matches the modified chip_io_openframe layout
in this PR (namely, the GPIO "_wrapped" pads are replaced with the
equivalent non-wrapped base cells).
 2023-09-25 20:10:37 -04:00
mo-hosni f5199a7475 add a gate-level for `chip_io_openframe` 2023-09-24 17:10:34 +03:00
mo-hosni cee0f31d91 add gate-level netlist for `caravel_openframe` 2023-09-18 16:59:55 +03:00
mo-hosni e2d21e5893 changed `caravel_logo`, `caravel_motto`, `copyright_block` to `caravan_logo`, `caravan_motto`, `copyright_block_a` respectively in `verilog/gl/caravan.v` to match the layout 2023-06-01 13:46:47 -07:00
Passant 1e46e15161 ~ update `caravan_core` to fix latch-up DRC violation (non MR) 2023-06-01 09:21:00 -07:00
mo-hosni e25997cc3b swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue 2023-05-30 22:33:33 -07:00
mo-hosni 0c78dbb954 Revert "reharden `caravan_core` to reduce the long wirelengths" 
This reverts commit de16ffc6b9.
 2023-05-30 04:35:59 -07:00
mo-hosni de16ffc6b9 reharden `caravan_core` to reduce the long wirelengths 2023-05-30 02:55:16 -07:00
mo-hosni e911784fb7 reharden `caravan_core` to fix LVS and timing issues 2023-05-29 20:07:08 -07:00
mo-hosni aeb0cbc45f reharden `caravan_core` to fix long wires issues 2023-05-29 02:50:45 -07:00
mo-hosni 8de897098d reharden `caravan_core`. Used a lib for the `user_analog_project_wrapper` and fixed DRCs. 2023-05-24 13:53:03 -07:00
mo-hosni fbf53572e1 reharden `housekeeping_alt` 2023-05-24 02:34:43 -07:00
mo-hosni 59cf3da287 add the analog connections in `caravan_core` GL 2023-05-24 00:42:28 -07:00
mo-hosni 3d9243e2cb update `caravan_signal_routing` to get aligned with `caravan_core` 2023-05-23 03:19:33 -07:00
mo-hosni 0c04656e52 add initial views for `caravan` 2023-05-23 03:05:18 -07:00
mo-hosni 26964d5460 add initial physical views for `caravan_core` 2023-05-23 02:16:44 -07:00
mo-hosni 3e7af79115 add `empty_macro_1` 2023-05-22 06:05:08 -07:00
mo-hosni 6b5aa27297 harden `housekeeping_alt` that will be integrated in `caravan_core` 2023-05-22 05:38:41 -07:00
marwaneltoukhy 1236f44456 updated physical verification reports 2023-04-26 17:33:44 +02:00
mo-hosni 907937b20f reharden `caravel_core` using the updated `gpio_defaults_block` 2023-04-20 23:17:38 -07:00
mo-hosni 2b8e7b7e2e reharden `caravel_core` to have `user_id_programming` as a macro 2023-04-20 07:26:58 -07:00
mo-hosni 94a68ad071 update the physical views for `caravel_core` as the previous ones had issues in integration 2023-04-11 07:43:05 -07:00
mo-hosni bd20921b90 reharden `caravel_core` using a newer OpenLane version 2023-04-10 07:14:59 -07:00
mo-hosni 4398773262 reharden `housekeeping` using a newer OpenLane version 2023-04-10 07:13:48 -07:00
mo-hosni 58bc32467d reharden `caravel_core` to fix 1 hold violation at the fast nominal corner. 2023-03-27 04:44:22 -07:00
mo-hosni 05795a470f reharden `caravel_core` 2023-03-26 02:56:12 -07:00
mo-hosni f233f2f708 reharden housekeeping to fix setup violations at the ss-max corner on top-level. 2023-03-13 02:53:49 -07:00
mo-hosni 360b7d4cf2 Reharden `caravel_core`. 2023-03-06 01:24:00 -08:00
mo-hosni bf18ce8985 remove old gate-level netlists. 2023-03-05 01:04:37 -08:00
mo-hosni 3ccbad56dd reharden `caravel_core`. 2023-03-05 00:59:13 -08:00
mo-hosni 725698014a reharden caravel_core after fixing an issue in the RTL of RAM256. 2023-02-28 05:51:06 -08:00
mo-hosni 7fdcd0d930 add missing GLs. 2023-02-27 11:44:04 -08:00
mo-hosni 7c6e956221 reharden caravel using the modified chip_io. 2023-02-27 11:19:33 -08:00
mo-hosni 9be48c6a7b implementation of caravel_core. 2023-02-27 10:38:06 -08:00
mo-hosni e560b56db5 reharden spare_logic_block. 2023-02-27 10:37:00 -08:00
mo-hosni 3f29ea49e7 harden mprj_io_buffer. 2023-02-27 10:33:48 -08:00
mo-hosni 5f8e954d95 reharden gpio_logic_high. 2023-02-27 10:29:46 -08:00
mo-hosni 86612d1f08 reharden caravel_clocking. 2023-02-27 10:26:19 -08:00
mo-hosni 7067304fd9 Added manual_power_connections. 2023-02-27 08:15:35 -08:00
mo-hosni 0952575c9d Add empty_macro which acts as a placement obstruction. 2023-02-27 08:14:55 -08:00
mo-hosni 8d6cfe6e2b reharden gpio_defaults_block. Changed the power stripes to be on Metal3. 2023-02-27 07:34:33 -08:00
mo-hosni 50a762407b re-implementation of housekeeping. Fixed maximum transition and antenna violations. 2023-02-27 07:30:03 -08:00
Kareem Farid d14035d8a2 gpio_signal_buffering rtl decaps 
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
 2022-11-01 19:16:53 +02:00
marwaneltoukhy c824608e25 Merge branch 'main' into caravel_redesign-2 2022-10-28 13:33:35 -07:00
mo-hosni b5010be8a7 Update Openlane views 2022-10-27 09:53:45 -07:00
mo-hosni 2d61e593aa Decreased distances from pins to and gates in mgmt_protect 2022-10-27 08:20:57 -07:00
Marwan Abbas 18d779f5cd removed caravel-eco.v gl netlist and added the eco for porb_h_in in caravel.v 2022-10-24 17:58:50 +02:00